Abstract: The invention provides a semiconductor device having a current input type pixel in which a signal write speed is increased and an effect of variations between adjacent transistors is reduced. When a set operation is performed (write a signal), a source drain voltage of one of two transistors connected in series becomes quite low, thus the set operation is performed to the other transistor. In an output operation, the two transistors operate as a multi-gate transistor, therefore, a current value in the output operation can be small. In other words, a current in the set operation can be large. Therefore, an effect of intersection capacitance and wiring resistance which are parasitic on a wiring and the like do not affect much, thereby the set operation can be performed rapidly. As one transistor is used in the set operation and the output operation, an effect of variations between adjacent transistors is lessened.

Abstract: A receiver is constructed by a signal reception circuit including a first amplifier section adapted to generate a first current in response to a first input signal and a second amplifier section adapted to generate a second current in response to a second input signal, to thereby generate an amplification signal in accordance with a difference between the first and second currents, and a feedback signal generating circuit adapted to generate a feedback signal in accordance with the amplification signal. Driving abilities of the first and second amplifier sections are determined in accordance with the feedback signal.

Abstract: A circularly polarized antenna includes a dielectric substrate, a closed-loop radiating element, a micro-strip radiating element, a feeding element, and a grounding element. The closed-loop radiating element is formed on a first surface of the dielectric substrate. The micro-strip radiating element is formed on the first surface of the dielectric substrate, is surrounded by the closed-loop radiating element, and is coupled to the closed-loop radiating element. The feeding element is formed on the first surface of the dielectric substrate, is surrounded by the closed-loop radiating element, and is coupled to the micro-strip radiating element. The grounding element is formed on a second surface of the dielectric substrate.

Abstract: A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.

Abstract: A voltage control oscillator (VCO) includes a VCO circuit and a back-gate coupling circuit, wherein the VCO circuit includes at least a first transistor, a second transistor and a resonant cavity formed by an inductor and a capacitor. The back-gate coupling circuit is formed by a plurality of capacitors and a plurality of resistors. In the embodiments of the present invention, the capacitors are coupled to the back-gate terminals of the first transistor and the second transistor, so as to reduce the power consumption and the phase noise of the VCO.

Abstract: A wideband monopole antenna arrangement, for a portable communication device, includes a substantially continuous conductor plate that includes a first antenna element and a second antenna element, and a signal ground arranged to interact with the antenna elements so as to form the wideband monopole antenna arrangement. The first antenna element extends substantially at an angle (?) with respect to the second antenna element. The angle (?) forms an acute angle of a right-angled triangle (T) in which the first antenna element extends substantially parallel to a hypotenuse (h) of the triangle (T) and the second antenna element extends substantially in parallel to a longer cathetus (c1) of two catheti (c1, c2) in the triangle (T).

Abstract: An input buffer circuit includes a voltage limiting circuit and a protection circuit coupled between a pull-up component and a pull-down component of a level detecting circuit. The voltage limiting circuit receives an input signal at a first voltage range and limits the input signal to a safe voltage range, the first voltage range being between an electrical ground and a first supply voltage level, and the safe voltage range being between the electrical ground and a second supply voltage level. The level detecting circuit has a pull-up component receiving the input signal directly from the input terminal and a pull-down component receiving the safe voltage range from the voltage limiting circuit. The level detecting circuit transitions the input signal from the first voltage range to the input signal at the second voltage range. The protection circuit is coupled in series between the pull-up component and the pull-down component so as to protect the level detecting circuit from gate oxide overstress.

Abstract: A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circuit, the first pinout, and the second pinout, controls the first pinout to be coupled to the first port or the second port, and controls the second pinout to be coupled to the first port or the second port.

Abstract: A driver circuit for a signal line of a large load is configured to include: a pMOS transistor having a source and a drain connected with a signal line and a ground line, respectively, and a gate receiving an input signal; and an nMOS transistor having a source and a drain connected with a signal line and a power supply line, respectively, and a gate receiving the input signal. As a result, the power consumption due to the signal line of a large load is reduced to realize a reduction of the power consumption of a semiconductor integrated circuit.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signals. The integrated circuit may further include control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and an ODT value selection signal on the ODT pin, the control logic further to control a length of termination based, at least in part, on the command. Other embodiments are described and claimed.

Abstract: An output buffer circuit includes a first output buffer section and a second output buffer section. The first output buffer section includes complementary semiconductors. The second output buffer section includes complementary semiconductors and is connected in parallel with the first output buffer section. The second output buffer section starts to output an second output signal after an output voltage of the output buffer circuit reaches a reference voltage indicative of one of an on-state and an off-state by a first output signal of the first output buffer section.

Abstract: A control circuit receives an external control signal in synchronism with an internal clock and generates an address signal and internal control signals. A data multiplexer has a plurality of input parallel lines and a plurality of output parallel lines and is switched to one of a first output state and a second output state in accordance with the internal control signal. In the first state, the data multiplexer outputs parallel data, which is input to the plurality of input parallel lines and read out from the memory core unit, to the plurality of output parallel lines corresponding to the plurality of input parallel lines. In the second state, the data multiplexer selects 1-bit data of the parallel data input to the plurality of input parallel lines and outputs the 1-bit data to the plurality of output parallel lines. A conversion circuit converts the parallel data into serial data.

Abstract: An integrated receiver circuit for amplifying an input signal based on a reference signal includes two voltage converters to respectively convert the input and reference signals to level-converted input and reference signals. An amplifier stage includes a PMOS input differential amplifier driven by the converted input and reference signals, and an NMOS input differential amplifier driven by the input and reference signals. The amplifier stage is connected to a first control stage to compensate an output offset current generated by the amplifier stage. A second control stage is cascaded to the first control stage to provide a duty cycle correction of an output signal. The receiver circuit ensures amplification of an input signal even if a level of the reference signal is close to a supply voltage, the input and reference signals have a large variation range, or the input signal has an asymmetrical input swing about the reference signal.

Abstract: In a data transmission circuit according to the present invention, selection circuits alternately switch between transistors of a main buffer and transistors of a dummy buffer. In high-speed data transmission, a H/L transmission switch circuit outputs high-speed data to a constant current driver and outputs a selection signal for inputting a control signal to the main buffer to a selection circuit. In low-speed data transmission, on the other hand, the H/L transmission switch circuit outputs a selection signal for inputting a control signal to the main buffer in accordance with the low-speed data to the selection circuit. The H/L transmission switch circuit controls an input of the control signal to the main buffer in accordance with the selection signal.

Abstract: An I/O output circuit is disclosed for interfacing a first system operating at a first voltage with a second system operating at a second voltage higher than the first voltage. The I/O output circuit includes an output stage module having one or more PMOS transistors and one or more NMOS transistors for coupling with the second system. A switch module is coupled to the output stage module for selectively providing the PMOS and NMOS transistors with various gate biases. A feedback circuit is coupled between an I/O pad that couples the output stage module to the second system and the switch module for controlling the switch module to generate the gate biases in response to a voltage at the I/O pad, thereby ensuring voltages across gates of the PMOS and NMOS transistors to be within a predetermined range.

Abstract: The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside an integrated circuit. An interconnection with four parallel transmission conductors plus a reference conductor has each of its ends connected to a termination circuit. The transmitting circuit receives at its input the signals of the four channels of the source and its output terminals are connected to the conductors of the interconnection. The receiving circuit's input terminals are connected to the conductors of the interconnection, and its four output channels are connected to the destination. The signals of the four channels of the source are sent to the four channels of the destination, without noticeable crosstalk.

Abstract: A high-speed interface between a first network component and a second network component includes a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the negative voltage input (VINN) by a positive input bus and a negative input bus, the negative voltage input (VINN) also coupled to a positive output circuit (OUTP). Implementing the high-speed interface calls for applying a bias to the a positive input bus and a negative input bus to periodically multiplex a data signal, thus providing a common receiving path for functional data and wrap data of the data signal.

Abstract: Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are circuits that are used, in conjunction with a software method, to generate test programs for testing exact I/O transitions for timing measurements at various operating conditions.

Abstract: A programmable logic device (PLD) includes a plurality of configurable resources, a programmable interconnect having a plurality of signal lines for providing a number of dedicated signal paths between any of the configurable resources, and a subway routing system having a shared subway bus coupled to the signal lines of the programmable interconnect at a plurality of connection points by a plurality of corresponding subway ports. The subway routing system, which provides alternate routing resources for the programmable interconnect, may be used to route different signals between different configurable resources at different times.

Abstract: Methods and apparatus for selectively allowing and disallowing changes to an impedance control signal applied to bus driver circuits coupling a device or system to a common, shared bus where impedance of the bus may vary over time. Well known impedance sensing circuits may be coupled to a common bus, such as a PCI bus, and may be used to generate an impedance control signal to be applied to well-known bus driver circuits, including, for example, PCI bus driver circuits, to vary the drive level of such bus driver circuits in accordance with the present electrical impedance sensed on the bus. Features and aspects hereof permit selectively allowing and disallowing changes to such impedance control signals as applied to the driver circuits based upon the present state of the bus and/or the present state of signals driven on the bus by the system embodying the features and aspects hereof.