Abstract: Pin-to-pin electro-static-discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A p-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-pin ESD test, power and ground are floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the floating ground bus. The gate node also turns on a shorting transistor that connects the floating ground bus to the floating substrate. A resistor drains the coupling capacitor to the substrate, rather than to ground. Current is injected into the substrate by the resistor. The snapback voltage is lowered by substrate-triggering.

Abstract: A method and apparatus for fault condition protection for a lighting control circuit is presented. The method consists of a hybrid software and hardware solution to take advantage of the useful attributes of both. In the event of a fault condition being detected the software set driving signals to the light are rapidly blocked via hardware. In the event the fault condition persists, software modifies the driving signals to the light.

Abstract: A battery protection circuit for use between a battery output and a load is achieved. The circuit comprises, first, a plurality of fused cells coupled in parallel between the battery output and the load. Each fused cell comprises, first, a fuse having first and second terminals where the first terminal is coupled to a battery output. Second, a means having zener effect has a p terminal and an n terminal. The p terminal is coupled to the second terminal of the fuse. Finally, a cell switch having first and second terminals completes each fused cell. The cell switch first terminal is coupled to the second terminal of the fuse, and the cell switch second terminal is coupled to the n terminal of the diode to form a cell output. Finally, the battery protection circuit comprises a shorting switch, that may comprise a MOS transistor that exhibits punch through, that is coupled between the load and each fused cell output. The current source second terminal is coupled to ground.

Abstract: An over-voltage protection module protects communications equipment against voltage surges, including periodic voltage disturbances. The protection module provides a steady state activation voltage threshold and a reduced activation voltage threshold less than the steady state value. Upon a receiving a periodic disturbance, the module activates initially upon receiving a voltage exceeding the steady state activation voltage threshold and activates for subsequent cycles of the disturbance upon receiving a voltage exceeding the reduced activation voltage threshold.

Abstract: A surge protection and reset circuit is provided for resetting a microprocessor to maintain a discharge lamp under a normal operating condition when the microprocessor is crashed owing to the cross talk or radiation effect in igniting a discharge lamp. The surge protection and reset circuit includes a ballast electrically connected to the discharge lamp for igniting the discharge lamp, a starting control circuit electrically connected to the ballast for triggering the ballast to ignite the discharge lamp and powering the ballast, a microprocessor electrically connected to the starting control circuit for initializing the starting control circuit when the microprocessor receives a lamp-state signal and a reset signal, and a reset circuit having an output terminal electrically connected to the microprocessor for providing the reset signal to reset the microprocessor when the reset circuit receives the lamp-state signal from a lamp-state terminal of the ballast.

Abstract: An electrostatic discharge (ESD) protection circuit includes an MOS transistor acting as a trigger for the circuit. A drain region of the MOS transistor is formed by an N-type heavily doped impurity region which overlaps an N-type well region. Further, a P-type heavily doped impurity region is formed in the N-type well region. The N-type and P-type heavily doped impurity regions are electrically connected to an input/output pad. The ESD protection circuit exhibits a reduced input capacitance at the pad, and a reduced breakdown voltage of the MOS transistor.

Abstract: An improved series-pass over-voltage protection circuit includes at least one N-channel enhancement mode MOSFET (NFET) coupling a DC voltage supply such as a motor vehicle storage battery to one or more high current electrical loads. The drain of the NFET is connected to the positive terminal of the DC voltage supply, and a high impedance gate voltage power supply biases the NFET to a fully enhanced state in normal operation to provide very low pass-through on-resistance.

Abstract: A plurality of electrodes in a solid object are located proximate to the contact interface between an ice layer and the surface of the solid object. A power source provides a potential difference across the electrodes to generate an electric field at the contact interface, thereby increasing the friction force between the solid object and the ice. Preferably, the power source is in AC power source. A capacitor in series between the power source and the electrodes creates an additional impedance for limiting the AC current to a level safe for human exposure.

Abstract: Air ionization apparatus includes a plurality of air ionizing electrodes connected to a source of high ionizing voltages, and includes a bias source connected to supply bias voltage to a reference electrode positioned near the air ionizing electrodes to alter the field gradients thereabout to selectively enhance production of positive or negative air ions in response to levels and polarity of bias voltage supplied to the reference electrode.

Abstract: An integrated circuit with at least one antenna for the contactless transmission of data or energy. The antenna is configured above and/or below circuit sections to be protected and, as part of a protective circuit, enables the integrated circuit to be monitored with regard to an undesirable external attack. Such an attack can be identified by the attempt to effect observation or manipulation from the outside, which are typically associated with an alteration of the physical properties of the antenna. These physical alterations lead to significant changes in the protective circuit signals that are transmitted via the antenna. These changes are identified by signal detectors and initiate a transfer of the integrated circuit into a security mode. In this case, in addition to the function as means for transmitting data and/or energy, the antenna also serves the function of being a protective shield of a protective circuit for the integrated circuit.

Abstract: The invention refers to a charge/discharge protection circuit for a rechargeable battery, where the protection circuit is integrated on a single chip, including the fusible link, the load current switch and the short-circuit switch. This is achieved by dividing the functions of the fusible link, the load current switch, and the short-circuit switch into in parallel arranged T-sections, each of which is designed for only a fraction of the nominal load so that each of the easily integrated fuse segments carry only the respective fraction of the nominal current. It is important that the entire protection circuit or its control logic will not be destroyed before through an unduly high over-voltage, in which case the sequential melting of the fuse segments would no longer be guaranteed. This is handled by a semiconductor switch which short-circuits the over-voltage immediately.

Abstract: A monitoring system monitors a microcomputer in which an angle calculator calculates the electrical angle of a motor using output signals from a rotation angle sensor. In the microcomputer, a control signal generator generates a coded control signal that indicates the range to which the calculated electrical angle belongs. In the monitoring system, the electrical angle detected by the rotation angle sensor is multiplied by an excitation signal provided for the rotation angle sensor, and an angle detector detects the resultant signals. Based on the detected signals, a supervisory signal generator outputs a coded supervisory signal that indicates the range to which the electrical angle detected by the rotation angle sensor belongs. Then a fault detector determines that a failure occurs in the microcomputer, if a comparator determines that the coded control signal disagrees with the coded supervisory signal.

Abstract: A high precision, high efficiency controller for LED devices such as LED arrays includes a current limiter, driver and buffer.

Abstract: Electrical receptacles configured to eliminate arc faults rather than merely detect such faults with attendant circuit disconnection, the invention contemplates low-cost, child-safe electrical receptacles useful in residential situations and which can be fitted within the confines of single gang enclosures. The safety receptacles of the invention can be used in all use situations including both residential and industrial applications to increase safe use of electrical receptacles in residential applications in particular and to decrease industrial liabilities. In essence, the safety receptacles of the invention prevent arcing during insertion of a plug into the receptacle, during residence of the plug in the receptacle and during removal of the plug from the receptacle with a substantial load to the receptacle.

Abstract: The protection circuit comprises a clamping circuit with a switching element for reducing a supply voltage in case of an over voltage condition, and a holding circuit for providing a holding current for the clamping circuit. The clamping circuit comprises a threshold circuit, which provides a switching voltage for a switching element when the supply voltage reaches an upper voltage limit. The switching element is connected to a charge capacitor, which provides the switching-on voltage for the switching transistor, and by reducing this supply voltage, the switching of the switching transistor is disabled. The holding circuit comprises in particular a capacitor, which is coupled via a resistor to the clamping circuit for providing an additional current in case of an over voltage condition.

Abstract: An electrostatic protection circuit of the present invention comprises: a first power supply terminal 1 to which a first voltage is applied; a second power supply terminal 2 to which a second voltage lower than the first voltage is applied; a first diode 12 connected in a reverse direction between the first and second power supply terminals; and a second diode 11 connected in a forward direction between the first and second power supply terminals. This configuration ensures that either one of the first and second diodes always operates in a forward direction to the static electricity applied between the first and second power supply terminals regardless of the polarity of the static electricity. Electrostatic charges therefore can be quickly absorbed through the diode in a forward direction.

Abstract: A double-triggered electrostatic discharge (ESD) protection circuit for coupling with a first voltage source and a second voltage source. The circuit includes a diode series and a transistor. The diode series comprises a plurality of serially connected diodes with the cathode of one diode connected to the anode of a subsequent diode. The positive terminal of the first diode in the diode series connects with the first voltage source. The gate terminal of the transistor connects with the anode of the last diode in the diode series. The substrate of the transistor connects with the cathode of the last diode in the diode series. The source terminal and the drain terminal of the transistor connect with the first voltage source and the second voltage source, respectively. By using double-triggered design, the ESD clamp device can be quickly triggered on to bypass ESD current.

Abstract: A power MOS transistor having a PMT chip located in a transistor housing in which the temperature of the transistor barrier junction is monitored is described. Protection of the PMT chip against overload and permanent damage is guaranteed without negatively affecting its switching function in that a protective circuit is provided in the transistor housing which directly measures the temperature of the transistor barrier junction using a temperature measuring element, and when a predefined or predefinable limit barrier junction temperature is reached reduces the drain current and thus the power loss of the PMT chip, the temperature measuring element being integrated in the PMT chip or accommodated in the transistor housing together with the protective circuit as an additional chip.

Abstract: A surge protector having a failsafe mechanism including at least one overvoltage protection element, at least one arm assembly, at least one ground element, at least one resilient member, and at least one protrusion. The at least one resilient member is electrically connected to the at least one ground element and the at least one protrusion is generally positioned between the at least one resilient member and the at least one arm assembly. The at least one protrusion is in thermal contact with the at least one resilient member, prevents the at least one resilient member from electrically contacting the at least one arm assembly during normal operation, and is spaced away from the at least one arm assembly.

Abstract: An electrostatic discharge prevention device enabled latch may be employed on or with an enclosure including an access panel. The electrostatic discharge prevention device enabled latch includes a latch for retaining the access panel in a closed position. The latch may be disengaged by operation of a latch release member which functions to effect release or disengagement of the latch. A conductor receptacle is attached to the enclosure, typically in the proximity of the access panel. An electrostatic discharge prevention device including a ground strap and a conductive terminal are provided for use by an individual desiring to gain access through the access panel to service enclosed components or circuits. When the conductive terminal is inserted into the conductor receptacle, a latch release member is displaced disengaging the latch.