Abstract: An adaptive electrical manifold is comprised of switchbox assemblies containing a plurality of non-volatile MEMS relay switches, apparatus for controlling these switches, and apparatus for controlling a daisy-chained group of switchbox assemblies.

Abstract: A three phase trip of a power line is prevented in a power distribution network delivering electrical power through multiple current carrying conductors and a neutral/ground line. The three phase trip is prevented after a change in the current in the neutral/ground line caused by a partial trip of a recloser. A partial trip is detected in the power distribution network, and then a threshold current is automatically adjusted from a first level to a second level for the neutral/ground line.

Abstract: The present invention proposes an ESD protection circuit and its related circuits, suitable in an integrated circuit (IC), and coupled between a first pad and a second pad. When a power supply is provided to the IC, a bias generator generates a bias voltage to close the protection component. When the power supply is not provided to the IC, the protection component is always on to release the ESD stress between the first pad and the second pad.

Abstract: An insulating member is used on or with a high-voltage probe that applies a voltage to the anode of a cathode ray tube during manufacture of the tube. If there are flaws in the frit seal of the tube, the probe produces arcing through the flaw into a grounded, conductive band disposed around the exterior of the frit seal. The insulating member is placed between the high-voltage probe tip and the grounded band around the frit seal. Consequently, the insulating member prevents electrical arcing external to the cathode ray tube between the high-voltage probe and the grounded band. Such arcing would otherwise interfere with the testing of the frit seal and could possibly damage the test equipment.

Abstract: The present invention includes an integrated circuit switch including a membrane supported over a first conductor on a substrate, a conductive region on the membrane and connecting to the first conductor on the substrate, a pulldown electrode on the substrate and under the membrane and a pillar to support the membrane after the pulldown threshold has been reached. A voltage greater than a pulldown threshold is applied between the membrane and the pulldown electrode will pull the membrane down to make a capacitive coupling to the first conductor. The addition of the pillars increases the upward restoring force when the activation voltage is removed.

Abstract: A chip assembly comprising a chip mounted on a support is disclosed. The chip assembly comprises at least one terminal and discharge means for discharging a charge accumulated on or transferred to the at least one terminal. The discharge means is connected to an RF common mode node for at least one circuit on the chip.

Abstract: A device inserted between a grounded poly-phase external voltage source and a load providing low insertion loss for differential mode currents and high insertion loss for ground currents. The device receives voltages from the grounded poly-phase external voltage source over atone or more voltage lines. The voltages contain common mode voltages. A filter connected to each of the voltage lines reduces the ground current from the load. A summing block adds the voltages from each of the voltage lines to generate a total common mode voltage. A ground referenced controlled voltage source generates a cancellation voltage equal to the total common mode voltage in response to the generation of total common mode voltage. The total common mode voltage is injected into the filter and substantially reduces the common mode voltage on each voltage line thereby substantially reducing the ground currents associated with each common mode voltage on each voltage line.

Abstract: A two-wire bus system for connecting a plurality of users has at least one damping circuit for damping line resonances in the two-wire bus system with respect to a reference potential. The damping characteristic of the damping circuit is selected such that the damping only becomes operative above a preestablished reference voltage threshold1 value. In this manner, it is achieved that a useful signal is not weakened by the damping circuit, but rather resonance voltages are damped only above the threshold value. It is advantageous if each of the users of the bus system has assigned to it a damping circuit.

Abstract: Electro-static-discharge (ESD) protection of an integrated circuit chip is enhanced by an EOS protection circuit using external components. An external MOSFET is placed in series with the ground pin of the integrated circuit chip. The external MOSFET has a gate coupled to a power bus through a gate resistor, and is bypassed by an ESD capacitor. The external MOSFET turns on after a delay when power is applied during hot insertion. The delay is determined by a power-to-ground bypass capacitor. The time delay of the on stage of the MOSFET inhibits ground current generated by EOS voltage leaked from the power supply through parasitic resistances, capacitances, and inductances, preventing ESD-protection diodes inside the chip from burning out from this EOS pulses that occur during hot insertion. The ESD bypass capacitor shunts the initial ESD pulse to ground before the external MOSFET turns on.

Abstract: A high voltage protection circuit (20) in a non-volatile memory includes a first transistor (22) and a second transistor (24) each formed in their own separate wells. A high voltage supply (Vhv) is provided at the drain of the second transistor (24). The source (40) of second transistor (24) is connected to the drain of first transistor (22) and to well (32), and the gate of the second transistor (24) is connected to Vdd, the main power supply to the chip. By forming the transistors in their own separate wells with the source of the second transistor (24) connected to its own well, breakdown of the circuit is governed by the sum of BVdss of the first transistor (22) and a gate induced breakdown (BVind) of the second transistor (24). With this circuit use of even a low Vdd (e.g. <3V) on the gate of the second transistor (24) is sufficient to protect against unwanted exposure to Vhs or to prevent leakage so that a higher stand-off voltage need not be generated and routed to the circuit.

Abstract: A varistor has a thermal fuse between a lead and an electrode. The fuse includes a link extending between the surface of an insulator and the fused electrode. The electrical connection of the link and the electrode is maintained by a low temperature solder fillet. That part of the link between the electrode and the insulator is surrounded by hot melt electrically insulating material. Upon sustained over-voltage conditions, the link and the solder fillet melt, and an insulating gap is rapidly created by molten hot melt material.

Abstract: An arc fault causes the line voltage across the line terminals of an arc fault circuit interrupter (AFCI) to change its characteristic voltage pulse shape as the line voltage is momentarily removed from the AFCI terminals after the arc extinguishes and before it re-strikes by introducing a flat voltage portion to the pulse shape. This flat voltage portion changes the voltage pulse width. An arc detector/processor detects this change in pulse width to produce a signal indicative of upstream (line side) arcing. The flat voltage portion can also be detected using clamping diodes and charging capacitors.

Abstract: A clamping MOS transistor-based overvoltage protection circuit is provided for a bidirectional transmission gate FET coupled between input and output ports. When the voltage applied to the input port exceeds the supply voltage by a MOS gate threshold, the clamping MOS transistor is turned on, pulling the voltage applied to the gate of the transmission gate FET very close to the applied overvoltage level by a voltage differential less than a diode drop. This reduction in Vgs of the transmission gate FET reduces its source-to-drain current, as the device operates deeper in a sub-threshold region, increasing the overvoltage rating for the same leakage current specification. In a second embodiment, a clamping MOS device is coupled on either side of the source-drain path of the transmission gate's FET device.

Abstract: A control circuit is provided for use in an electromagnetic device with a coil where the electromagnetic device is actuated with an actuating current and held in an operative condition by a holding current with the holding current being significantly lower in magnitude than the actuating current. The control circuit includes first and second transistors wherein, during a powered mode, the first transistor is disposed in an on state and the second transistor is disposed in an off state, and, during a shorted mode, the first transistor is disposed in an off state and the second transistor is disposed in an on state. Additionally, a power source selectively communicates with the coil, and during a first time interval, the power source communicates with the coil in the powered mode and, during a second time interval, the power source is disconnected from the coil in the shorted mode.

Abstract: A protection device connected between hot and neutral conductors of an AC power line includes a fault detection circuit which controls a breaker coil operatively associated with a set of interrupting contacts. A capacitance circuit connected between the hot conductor and the neutral conductor stores a charge of a polarity indicative of a line-load miswire. This stored charge independently activates the set of interrupting contacts when the interrupting contacts are closed and the device is miswired, thus preventing the miswired device from providing power.

Abstract: A semiconductor device (10) includes a protection circuit (12) that has an input (24) for activating the protection circuit in response to a sampling pulse (VENABLE) to detect a fault condition of the semiconductor device, and an output (30) for producing a control signal (VCONTROL1) when a fault condition is detected.

Abstract: Damage to electronic golf course sprinkler valve controls from lightning current surges is prevented by electrically isolating the actual valve control circuit from the logic circuitry that controls it, using in the valve control circuit only components and printed traces that can withstand at least as much power dissipation as the field wiring, and grounding each valve control individually to earth ground through a plasma discharge device.

Abstract: This invention includes a circuit that approximates the thermal behavior of a fuse or other electronic device that is coupled in series with the circuit. In one preferred embodiment, the circuit protects a fuse coupled in series with a rechargeable battery from clearing during soft short conditions. Thus, when the instantaneous current is temporarily above the current rating of the fuse, yet the root mean squared current is below the current rating of the fuse, the circuit works to estimate the heating of the fuse element and limit the current to a root mean squared value that is less than the current rating of the fuse. One embodiment includes a programmable comparator that actuates a counter which, in turn, increments to estimate heating of the element when the current exceeds a predetermined threshold.

Abstract: An electrical ground (10) for use in a spacecraft comprising, a first surface (12) capable of emitting electrons by photoemission, at least one isolated conductive surface (18) and at least one conductive connector (20) in connection with the first surface (12) and the isolated conductive surface (18) such that excess electrical charge developed in the isolated conductive surface (18) is dispersed into the first surface (12).