Patents Examined by James G Norman
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Patent number: 11545213Abstract: The disclosure provides a novel system and method of storing multi-bit information, including providing a nano-channel-based polymer memory device, the device having at least one memory cell comprising at least two addition nano-channels, each of the addition nano-channels arranged to add a unique chemical construct (or codes) to the polymer when the polymer enters the respective addition nano-channel, the polymer having a bead or origami on a non-writing end of the polymer; each nano-channel having a nano-port constriction having a port width which allows the polymer to pass through the nano-port, and does not allow the bead or origami to pass through and does not allow addition or deblocking enzymes (or beads attached thereto) to pass through the nano-port; successively steering the polymer through the nanopore into the addition nano-channels to add the codes to the polymer based on a predetermined digital data pattern to create the digital data pattern on the polymer.Type: GrantFiled: August 6, 2021Date of Patent: January 3, 2023Assignee: IRIDIA, INC.Inventor: Paul F. Predki
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Patent number: 11521988Abstract: Implementations of the present disclosure provide 3D memory devices and methods for operating the 3D memory devices. In an example, a 3D memory device includes a plurality of memory layers and a dummy memory layer between the plurality of memory layers and a NAND memory string extending through the memory layers and the dummy memory layer. The NAND memory string includes a source, a drain, and a plurality of memory cells at intersections with the plurality of memory layers and between the source and the drain. The 3D memory device also includes a peripheral circuit configured to erase the plurality of memory cells. To erase the plurality of memory cells, the peripheral circuit includes a word line driving circuit configured to apply a positive bias voltage on the dummy memory layer.Type: GrantFiled: March 26, 2021Date of Patent: December 6, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Shiyu Xia, Feng Xu, Lei Jin, Jie Yuan, Xuezhun Xie, Wenqiang Chen
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Patent number: 11514965Abstract: A resistive memory device is provided. The resistive memory device includes a bitline, a source line, a memory cell electrically connected to the bitline and the source line by a first switch, a first transistor electrically connected to the bitline, a second transistor electrically connected to the source line, a gate voltage generator configured to generate a first gate voltage that is provided to a gate electrode of the first transistor, and configured to generate a second gate voltage that is provided to a gate electrode of the second transistor and a second switch that provides the first and second gate voltages to the gate electrodes of the first and second transistors.Type: GrantFiled: May 25, 2021Date of Patent: November 29, 2022Inventor: Artur Antonyan
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Patent number: 11501811Abstract: In a memory, a first node holds first data from a first cell. A second node holds second data from a second cell near the first cell. A differential circuit includes a first current path passing a first current corresponding to a voltage of the first node and a second current path passing a second current corresponding to a voltage of the second node, and outputs an output signal corresponding to a voltage difference between the first and the second nodes from an output part. A first register latches the output signal and output the signal as a hold signal. A first offset part is connected to the first current path and offsets the first current when the hold signal has a first logic level. A second offset part is connected to the second current path and offsets the second current when the hold signal has a second logic level.Type: GrantFiled: June 17, 2021Date of Patent: November 15, 2022Assignee: KIOXIA CORPORATIONInventor: Kosuke Hatsuda
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Patent number: 11495288Abstract: A disclosed sense circuit for a memory circuit includes sense amplifiers that detect differences in voltage levels on complementary bitlines during read operations. Instead of the sense amplifiers having built-in footer devices that lead to significant leakage, the sense circuit incorporates a common footer device for all sense amplifiers. To ensure that this footer device has sufficient drive strength to enable voltage differential detection by each sense amplifier, the sense circuit also includes a sense signal generation and boost circuit (SSG&B circuit) that generates a sense mode control signal (SEN) to control the on/off states of the footer device and that further boosts SEN, at the appropriate time, to increase the drive current. By using the common footer device and the SSG&B circuit, leakage from the sense circuit is reduced during a pre-charge operation mode without sacrificing performance during a read operation mode. Also disclosed are associated method embodiments.Type: GrantFiled: January 7, 2021Date of Patent: November 8, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Vivek Raj, Shivraj G. Dharne, Uttam K. Saha, Mahbub Rashed
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Patent number: 11475942Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.Type: GrantFiled: January 21, 2021Date of Patent: October 18, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Wei Wang, Chia-Hao Pao, Choh Fei Yeap, Yu-Kuan Lin, Kian-Long Lim
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Patent number: 11475937Abstract: Methods, systems, and devices for die voltage regulation are described. A device may include a first die and second die. A component that generates voltage on the first die may be connected to a capacitor on the second die through a conductive line. The conductive line may allow the capacitor on the second die to regulate voltage generated by the component on the first die.Type: GrantFiled: June 3, 2021Date of Patent: October 18, 2022Assignee: Micron Technology, Inc.Inventors: Taeksang Song, Saira S. Malik, Hyunyoo Lee, Kang-Yong Kim
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Patent number: 11475941Abstract: The present disclosure relates to a structure including a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.Type: GrantFiled: December 3, 2020Date of Patent: October 18, 2022Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Akhilesh R. Jaiswal, Bipul C. Paul, Steven R. Soss
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Patent number: 11475971Abstract: A semiconductor device includes a control circuit configured to generate an input enable signal, an output enable signal, a latch control signal, and an error correction control signal based on a write control signal, a write check command, and a read check command for performing an error correction test mode; a latch circuit configured to generate latch data, a latch parity, and a latch masking signal by latching input data, an input parity, and an input masking signal and configured to re-store corrected data as the latch data, during a period in which the latch control signal is enabled; and an error correction circuit configured to generate the corrected data by correcting an error, included in the latch data, based on the latch data, the latch parity and the latch masking signal during a period in which the error correction control signal is enabled.Type: GrantFiled: June 21, 2021Date of Patent: October 18, 2022Assignee: SK hynix Inc.Inventor: Keun Kook Kim
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Patent number: 11456046Abstract: A clock locking method of a memory device, may include performing an initial locking operation in a delay locked loop circuit before an internal voltage is stabilized, monitoring clock skew between a reference clock and a feedback clock using a window detection circuit after the internal voltage is stabilized, and performing a re-locking operation in the delay locked loop circuit using a dynamic delay control corresponding to the clock skew.Type: GrantFiled: April 8, 2021Date of Patent: September 27, 2022Assignee: Samsung Electronics Co., Ltd.Inventor: Hundae Choi
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Patent number: 11449442Abstract: An example printing method can involve a memory buffer of a printing system containing image data, and the method can include (i) issuing, by an initiator of the printing system, a single read-then-clear memory command; (ii) receiving, by a memory controller of the printing system, the single read-then-clear memory command; and (iii) in response to receiving the single read-then-clear memory command, the memory controller both (a) reading the image data from the memory buffer of the printing system and (b) after reading the image data, clearing the image data from the memory buffer of the printing system.Type: GrantFiled: March 13, 2020Date of Patent: September 20, 2022Assignee: KYOCERA Document Solutions Inc.Inventors: Kenneth Allen Schmidt, Kendrick Esperanza Wong
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Patent number: 11442872Abstract: Techniques described herein are related to protecting at least a portion of data stored in a memory array. A method may include detecting an invalid memory access request based at least in part on the secret key and the identifier and preventing unauthorized access of a memory array by halting an internal refresh of one or more memory cells associated with the memory array in response to detecting the invalid memory access request.Type: GrantFiled: August 20, 2019Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventor: Harish N. Venkata
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Patent number: 11443790Abstract: A magnetoresistive memory device includes a first electrode, a second electrode that is spaced from the first electrode, and a perpendicular magnetic tunnel junction layer stack located between the first electrode and the second electrode. The perpendicular magnetic tunnel junction layer stack includes, from one side to another: a reference layer having a fixed reference magnetization direction, a first spinel layer located including a first polycrystalline spinel material having (001) texture along an axial direction that is perpendicular to an interface with the reference layer, a magnesium oxide layer including a polycrystalline magnesium oxide material having (001) texture along the axial direction, a second spinel layer including a second polycrystalline spinel material having (001) texture along the axial direction, and a ferromagnetic free layer.Type: GrantFiled: March 4, 2021Date of Patent: September 13, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Bhagwati Prasad, Derek Stewart, Matthew Carey, Tiffany Santos
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Patent number: 11437109Abstract: A semiconductor storage device includes memory strings, bit lines connected to the memory strings, respectively, sense transistors of which gates are connected to the bit lines, respectively, first transistors connected between the bit lines and the gates of the sense transistors, respectively, and a control circuit. Each of the memory strings includes first and second memory transistors adjacent to each other. The control circuit is configured to perform, during a first write sequence, a read operation with respect to the second memory transistors, a program operation with respect to the first memory transistors, and a verify operation with respect to the first memory transistors, in this order. During the verify operation, the control circuit turns on the first transistors during a first sense period, and then turns on the first transistors during a second sense period longer than the first sense period.Type: GrantFiled: March 1, 2021Date of Patent: September 6, 2022Assignee: KIOXIA CORPORATIONInventor: Keita Kimura
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Patent number: 11437381Abstract: Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.Type: GrantFiled: February 10, 2020Date of Patent: September 6, 2022Assignee: Micron Technology, Inc.Inventors: Jiyun Li, Scott J. Derner
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Patent number: 11430514Abstract: An electronic circuit includes a plurality of word lines; a plurality of bit lines intersecting the plurality of word lines at a plurality of grid points; and a plurality of resistive random-access memory cells located at the plurality of grid points. Each of the resistive random-access memory cells includes a top metal coupled to one of: a corresponding one of the word lines and a corresponding one of the bit lines; a bottom metal coupled to another one of: the corresponding one of the word lines and the corresponding one of the bit lines; a dielectric sandwiched between the top metal and the bottom metal; and a high-resistance semiconductive spacer electrically connecting the top metal and the bottom metal in parallel with the dielectric.Type: GrantFiled: January 12, 2021Date of Patent: August 30, 2022Assignee: International Business Machines CorporationInventors: Youngseok Kim, Soon-Cheon Seo, Choonghyun Lee, Injo Ok, Alexander Reznicek
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Patent number: 11423981Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memory array. The first vertical n-type transistor may be configured to selectively couple an access line with a source node and the second n-type transistor may be configured to selectively couple the access line with a ground node. To activate the access line coupled with the first and second vertical n-type transistors, the first vertical n-type transistor may be activated, the second vertical n-type transistor may be deactivated, and the source node coupled with the first vertical n-type transistor may have a voltage applied that differs from a ground voltage.Type: GrantFiled: December 10, 2020Date of Patent: August 23, 2022Assignee: Micron Technology, Inc.Inventors: Paolo Fantini, Lorenzo Fratin, Fabio Pellizzer
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Patent number: 11417378Abstract: An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.Type: GrantFiled: March 12, 2019Date of Patent: August 16, 2022Assignee: TOHOKU UNIVERSITYInventors: Tetsuo Endoh, Shoji Ikeda, Hiroki Koike
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Patent number: 11410708Abstract: Provided herein is a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a contact pattern including a vertical contact part, and a sidewall contact part extending from the vertical contact part in a direction crossing the vertical contact part, a lower conductive pattern having a hole into which the vertical contact part is inserted, and an upper conductive pattern overlapping a portion of the lower conductive pattern. The upper conductive pattern includes a first side portion in contact with the sidewall contact part, and a second side portion facing the vertical contact part and spaced apart from the vertical contact part.Type: GrantFiled: May 27, 2020Date of Patent: August 9, 2022Assignee: SK hynix Inc.Inventor: Nam Jae Lee
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Patent number: 11404479Abstract: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.Type: GrantFiled: December 15, 2020Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventors: Andrea Redaelli, Agostino Pirovano