Patents Examined by James G Norman
  • Patent number: 11176972
    Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sanjeev Kumar Jain, Jaspal Singh Shah
  • Patent number: 11176981
    Abstract: A magnetoresistive memory device includes first electrode, a second electrode that is spaced from the first electrode, and a perpendicular magnetic tunnel junction layer stack located between the first electrode and the second electrode. The perpendicular magnetic tunnel junction layer stack includes a first texture-breaking nonmagnetic layer including a first nonmagnetic transition metal, a second texture-breaking nonmagnetic layer including a second nonmagnetic transition metal, a magnesium oxide dielectric layer located between the first and second texture-breaking nonmagnetic layers, a reference layer located between the first and second texture-breaking nonmagnetic layers, a free layer located between the first and second texture-breaking nonmagnetic layers, and a spinel layer located between the reference layer and the free layer, and including a polycrystalline spinel material having (001) texture along an axial direction extending between the reference layer and the free layer.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 16, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Bhagwati Prasad, Derek Stewart, Bruce Terris
  • Patent number: 11176976
    Abstract: A semiconductor memory device includes a read/write control circuit and an error correction circuit. The read/write control circuit generates an internal write signal after generating an internal read signal from one of a plurality of shifted signals which are generated by shifting a read-modify-write command according to a frequency of a clock signal. The error correction circuit corrects an error included in internal data by performing a logical operation of read data generated by the internal read signal and the internal data to generate write data. The internal read signal is enabled by a write set signal during the read-modify-write operation.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: November 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11170824
    Abstract: A semiconductor memory includes: a first line; a second line spaced apart from the first line and extending in a first direction; a third line spaced apart from the second line and extending in a second direction; a first memory cell disposed between the first and second lines at an intersection region of the first and second lines, the first memory cell including a first selection element layer, a first electrode, and a first insert electrode interposed between the first selection element layer and the first electrode; and a second memory cell disposed between the second and third lines at an intersection region of the second and third lines, the second memory cell including a second selection element layer, a second electrode, and a second insert electrode interposed between the second selection element layer and the second electrode.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Myoung-Sub Kim, Tae-Hoon Kim, Hye-Jung Choi, Seok-Man Hong
  • Patent number: 11164888
    Abstract: A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 2, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Takuya Futatsuyama, Go Shikata
  • Patent number: 11164617
    Abstract: A memory system and an operating method thereof are provided. The memory system includes a plurality of pseudo static random access memory chips and a memory controller. The pseudo static random access memory chips are coupled to each other. When receiving an action command, each of the pseudo static random access memory chips determines whether a refresh collision occurs in itself, and generates a collision signal accordingly. The memory controller controls the pseudo static random access memory chips according to the collision signal. All of the pseudo static random access memory chips share their respective collision signals to perform a same latency synchronously.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Hitoshi Ikeda
  • Patent number: 11139001
    Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Scott E. Sills
  • Patent number: 11133066
    Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: September 28, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Yuki Shimizu, Yoshihiko Kamata, Tsukasa Kobayashi, Hideyuki Kataoka, Koji Kato, Takumi Fujimoto, Yoshinao Suzuki, Yuui Shimizu
  • Patent number: 11127446
    Abstract: Embodiments of a Stochastic memristive array (SMA) device based on arrays of voltage-controlled magnetic tunnel junctions (MTJs) are disclosed. The SMA device is based on an array of stochastic (low energy barrier) magnetic tunnel junctions that are connected in parallel which simultaneously exhibits features that include (i) stochasticity and (ii) memristive behavior. The energy barrier of the MJTs may be tuned by an applied voltage (electric field). SMA devices may find applications in emerging computing concepts such as probabilistic computing and memcomputing, among others, providing a pathway towards intelligent hybrid CMOS-spintronic systems.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: September 21, 2021
    Assignee: NORTHWESTERN UNIVERSITY
    Inventors: Pedram Khalili Amiri, Giovanni Finocchio
  • Patent number: 11127482
    Abstract: As described, a device may include detection circuitry to detect a deck of a memory array. The deck may include a conductive identifier coupled between a logic high voltage node and the detection circuitry a control circuit coupled to the detection circuit. The control circuit may perform operations including transmitting a test enable signal to the detection circuitry. The detection circuitry may generate a valid signal indicative of an existence of the conductive identifier of the deck in response to the test enable signal. The operations may also include the control circuit receiving the valid signal from the detection circuitry and adjusting a memory operation associated with the memory array based at least in part on the valid signal.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bret Addison Johnson, Vijayakrishna J. Vankayala
  • Patent number: 11127751
    Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation, and biasing the back gate while biasing the bit line and the word line.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Andrew Bicksler, Marc Aoulaiche, Albert Fayrushin
  • Patent number: 11111782
    Abstract: The present invention relates to an oilfield management system. The oilfield management system comprises: one or more devices for measuring working conditions of oil wells, the one or more devices for measuring working conditions of oil wells are installed on one or more oil wells respectively for measuring working conditions of the one or more oil wells, the working conditions of oil wells at least comprise indicator diagrams of oil wells; one or more remote transmission units, each of the remote transmission units receives the working conditions measured by one or more of the devices for measuring working conditions of oil wells; and server, which determines running status of the one or more oil wells according to the working conditions of oil wells from the one or more remote transmission units; maintenance staff or administrators manage the one or more oil wells according to the running status of the one or more oil wells.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: September 7, 2021
    Inventor: Xinhua Li
  • Patent number: 11114150
    Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: September 7, 2021
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, John Eric Linstadt, Liji Gopalakrishnan
  • Patent number: 11107537
    Abstract: A non-volatile memory includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array region in the memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines in the memory cell region, an outer memory cell string in the memory cell region including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O) circuit in the peripheral circuit region including a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: August 31, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su Chang Jeon, Seung Bum Kim, Ji Young Lee
  • Patent number: 11099773
    Abstract: A memory system includes a memory device and a controller. The controller receives data from a host, allocates buffers after a throttling delay, buffers the data in the buffers, provides the buffered data to the memory device for a write operation, generates a response associated with the write operation, and transmits the response to the host. The controller inserts a throttling delay before allocating the buffers and/or transmitting the response. The throttling delay is determined based on a time elapsed since providing previously buffered data to the memory device and the size of the buffered data. The throttling delay is corrected based on the difference of the number of currently allocated buffers and a buffer reserve threshold.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventor: Siarhei Kryvaltsevich
  • Patent number: 11087808
    Abstract: Provided is a word-line structure including a substrate, a word line, and an epitaxial pattern. The word line is embedded in the substrate. The word line includes a conductive layer, a barrier layer, an insulating layer, and a gate dielectric layer. The barrier wraps a lower portion of the conductive layer. The insulating layer wraps an upper portion of the conductive layer. The gate dielectric layer surrounds the insulating layer and the barrier layer to electrically isolate the barrier layer from the substrate. The epitaxial pattern is disposed between the insulating layer and the substrate and in contact with the substrate. A memory device including the word-line structure and a method of manufacturing the same are also provided.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 10, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Li-Ting Wang, Ming-Chung Chiang
  • Patent number: 11087829
    Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James S. Rehmeyer, George B. Raad, Debra M. Bell, Markus H. Geiger, Anthony D. Veches
  • Patent number: 11075637
    Abstract: A signal generation circuit is disclosed according to an embodiment of the invention. The signal generation circuit includes a phase control circuit, a bias control circuit and a phase interpolation circuit. The phase control circuit is configured to generate a phase control signal according to a phase adjustment signal. The bias control circuit is configured to generate a bias voltage according to the phase control signal. The phase interpolation circuit is configured to generate a clock signal according to the phase control signal and the bias voltage. The bias voltage is used to adjust a current of the phase interpolation circuit to correct an error of the clock signal.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: July 27, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Jen-Chu Wu, Yu-Chiang Liao
  • Patent number: 11069745
    Abstract: According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: July 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenichi Murooka
  • Patent number: 11062775
    Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: July 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park