Patents Examined by James G Norman
  • Memory device and operating method thereof
    Patent number: 10706932
    Abstract: A memory device prevents generation of an abnormal column address. The memory device includes: a memory cell array; and a column address controller configured to generate a column address of the memory cell array in response to a column address control signal, wherein the column address controller enables the column address control signal when an address signal is input, and wherein the address signal includes a column address signal corresponding to the column address.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Eun Kyu In, Jae Woo Park, Seok Won Park, Byung Ryul Kim
  • Semiconductor memory devices and methods of operating semiconductor memory devices
    Patent number: 10706953
    Abstract: A semiconductor memory device includes a memory cell array and an address decoder. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word-lines and bit-lines, each of the plurality of memory blocks are divided into a plurality of row blocks by row block identity bits of a row address, and each of the of row blocks includes a plurality of sub-array blocks arranged in a first direction. The address decoder changes a physical row address of a memory cell that stores or outputs data based on a column address received with a write command or a read command.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Jin Cho, Tae-Young Oh, Jung-Hwan Park
  • Resistive memory sensing
    Patent number: 10699784
    Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu, Lei Bi, Adam D. Johnson, Brent Keeth, Alessandro Calderoni, Scott E. Sills
  • Semiconductor device
    Patent number: 10692586
    Abstract: A semiconductor device is disclosed, which is configured to perform a test using various conditions during a test mode. The semiconductor device includes a voltage generation circuit configured to output 2n (n is an integer of n?2) bit-line precharge voltages through different power-supply lines, based on a mode control signal, and a sense amplifier configured to receive the bit-line precharge voltages from the voltage generation circuit, and supply the 2n bit-line precharge voltages to corresponding bit lines in units of 2n successive bit-lines within the same cell array.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 23, 2020
    Assignee: SK hynix Inc.
    Inventors: Jae Hwan Seo, Sung Soo Chi
  • Semiconductor devices and operations thereof
    Patent number: 10685697
    Abstract: A semiconductor device may be provided. The semiconductor device may include a power-down signal generation circuit and a refresh signal generation circuit. The power-down signal generation circuit may be configured to generate a power-down signal which is enabled during a power-down operation period based on a multi-operation signal that is generated by decoding commands. The refresh signal generation circuit may be configured to generate a refresh signal which is enabled during a refresh operation period based on the multi-operation signal and an operation selection signal.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: June 16, 2020
    Assignee: SK hynix Inc.
    Inventors: Ki Hun Kwon, Jae Il Kim
  • Magnetoresistance effect element
    Patent number: 10685671
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, and the tunnel barrier layer has a spinel structure represented by a composition formula AGa2Ox (0<x?4), and an A-site is a non-magnetic divalent cation which is one or more selected from a group consisting of magnesium, zinc and cadmium.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 16, 2020
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Katsuyuki Nakada, Tatsuo Shibata
  • Semiconductor device
    Patent number: 10679710
    Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.
    Type: Grant
    Filed: September 2, 2018
    Date of Patent: June 9, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiro Hirashima, Masaru Koyanagi, Mikihiko Ito, Kei Shiraishi, Fumiya Watanabe
  • Semiconductor storage device
    Patent number: 10679713
    Abstract: A semiconductor storage device comprises a memory block including first and second memory cells, first and second word lines electrically connected to the first and second memory cells, respectively, first and second booster circuits, and a control circuit. During a read operation in which the first word line is a selected word line, the control circuit controls the first booster circuit to start boosting the output voltage thereof before a target block address associated with the read command is determined, causes the output voltage of the first booster circuit to be supplied to the first and second word lines, controls the second booster circuit to start boosting the output voltage thereof, and causes the output voltage of the second booster circuit, instead of the output voltage of the first booster circuit, to be supplied to the first word line.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: June 9, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Sanad Bushnaq, Toshifumi Hashimoto
  • Circuit-protection devices
    Patent number: 10679982
    Abstract: Circuit-protection devices may include first and second circuit-protection units, a first gate having a first source/drain connected to a first node of the first circuit-protection unit, and a second gate having a first source/drain connected to a first node of the second circuit-protection unit, wherein a second source/drain of the first gate is connected to a second source/drain of the second gate.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michael Smith
  • Semiconductor memory device
    Patent number: 10672473
    Abstract: A semiconductor memory device includes a first conductor that extends in a first direction, a second conductor that extends in a second direction, a first memory cell connected between the first conductor and the second conductor and including a phase change element, and a control circuit. The control circuit applies a first voltage across the first memory cell via the first conductor and the second conductor during a first period of time of a write operation targeted to the first memory cell, and a second voltage across the first memory cell via the first conductor and the second conductor during a second period of time of the write operation after the first period. The first voltage is an overshoot voltage. The second voltage is a preset voltage having a magnitude sufficient to place the phase change element in a molten state during the second period of time.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: June 2, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takaaki Nakazato, Atsushi Kawasumi
  • Semiconductor devices, and related control logic assemblies, electronic systems, and methods
    Patent number: 10672432
    Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Scott E. Sills
  • Three dimensional memory devices
    Patent number: 10672456
    Abstract: Systems and methods using a three-dimensional memory device with a number of memory cells disposed vertically in a number of pillars arranged along a horizontal direction can be used in a variety of applications. In various embodiments, pillars of memory cells may be disposed between lower and upper digitlines respectively coupled to different sense amplifiers to provide read/write operations and refresh operations. In various embodiments, a three-dimensional memory device having an array of memory cells vertically arranged in pillars may include a sense amplifier and digitline with a static random access memory cache, where the static random access memory cache is disposed below the array of memory cells in the same die. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fredrick David Fishburn, Charles L. Ingalls
  • Segmented memory and operation
    Patent number: 10672477
    Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of series-connected memory cells of the plurality of strings of series-connected memory cells may be selectively connected to a common data line through a corresponding respective select gate, a first set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a second set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Toru Tanzawa, Han Zhao
  • Memory component with independently enabled data and command interfaces
    Patent number: 10665289
    Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 26, 2020
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Lei Luo, Liji Gopalakrishnan
  • Semiconductor memory device
    Patent number: 10665308
    Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of pages; a voltage supply unit configured to provide operating voltages to the plurality of pages; a plurality of page buffers coupled to a plurality of bit lines of the memory cell array and configured to control and sense currents flowing through the plurality of bit lines in response to a page buffer sensing signal; and a control logic configured to control the voltage supply unit and the plurality of page buffers such that the plurality of pages are successively programmed, and to control a potential level of the page buffer sensing signal depending on a program sequence of the plurality of pages during a program verify operation of a program operation.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventor: Won Hee Lee
  • High gain sense amplifier with offset cancellation for magnetoresistive random access memory
    Patent number: 10658022
    Abstract: A magnetoresistive random access memory (MRAM) system is described. The system includes a sense amplifier that performs a two-phase read, including a first phase in which a first n-channel transistor is coupled to a reference resistance and a second n-channel transistor is coupled to a data resistance, and a second phase in which the first n-channel transistor is coupled to the data resistance and the second n-channel transistor is coupled to the reference resistance. The circuit further includes a first active amplifier for controlling a gate voltage of the first n-channel transistor and a second active amplifier for controlling a gate voltage of the second n-channel transistor. The circuit further includes a comparator configured to output the data state of the cell based on input of a first voltage related to a reference resistance and a second voltage related to a data resistance.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventor: Thomas Martin Maffitt
  • Nonvolatile memory device and storage device including nonvolatile memory device
    Patent number: 10658040
    Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park
  • Memory devices with distributed block select for a vertical string driver tile architecture
    Patent number: 10650895
    Abstract: Memory device having a tile architecture are disclosed. The memory device may include a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry. Another memory device may include a memory array, and a CMOS under array region. At least some tile regions may include portions of a total amount of block select circuitry distributed throughout the CUA region, vertical string drivers located outside of the memory array, and page buffer circuitry coupled with the memory array. Another memory device may include a first tile pair including a first tile, a second tile, a first vertical string driver therebetween, a first page buffer region that is greater than 50% of area for the first tile pair, and a first portion of a distributed block select circuitry.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Eric N. Lee
  • Semiconductor devices and operations thereof
    Patent number: 10650880
    Abstract: A semiconductor device may be provided. The semiconductor device may include a power-down signal generation circuit and a refresh signal generation circuit. The power-down signal generation circuit may be configured to generate a power-down signal which is enabled during a power-down operation period based on a multi-operation signal that is generated by decoding commands. The refresh signal generation circuit may be configured to generate a refresh signal which is enabled during a refresh operation period based on the multi-operation signal and an operation selection signal.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: May 12, 2020
    Assignee: SK hynix Inc.
    Inventors: Ki Hun Kwon, Jae Il Kim
  • Control circuit and control method for pseudo static random access memory
    Patent number: 10643689
    Abstract: A control circuit and a control method for a pseudo static random access memory are provided. The control circuit counts a number of latch times of data based on an external clock to generate a first count value, counts a number of write times of the data based on an asynchronous column address strobe clock to generate a second count value, and compares the first count value and the second count value. The control circuit provides a column address strobe clock according to the asynchronous column address strobe clock in an asynchronous mode. At the time of a first occurrence of the first count value being equal to the second count value, the control circuit enters a write operation into a synchronous mode from the asynchronous mode to adjust a period of the asynchronous column address strobe clock to a period of the external clock.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: May 5, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Hitoshi Ikeda