Abstract: Devices and methods include distributing biases for input buffers of a memory device. The devices include multiple input buffers configured to buffer data for storage in the multiple memory banks. The devices also include biasing generation and distribution circuitry configured to generate and distribute biases to the multiple input buffers. The biasing generation and distribution circuitry includes bias voltage generation circuitry and multiple remote resistor stacks each located at a corresponding input buffer of the input buffers and remote from the bias voltage generation circuitry.

Abstract: Apparatus having an array of memory cells might include a first transistor having a control gate, a first source/drain connected to a first contact for connection to peripheral circuitry, and a second source/drain connected to a second contact for connection to a data line selectively connected to a respective set of strings of series-connected memory cells of the array of memory cells; and a second transistor having a control gate, a first source/drain connected to the second contact, and a second source/drain connected to a third contact for connection to a common source selectively connected to each string of series-connected memory cells of the respective set of strings of series-connected memory cells for the data line.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: A semiconductor memory includes: a first line; a second line; a third line; a first memory cell disposed between the first line and the second line at an intersection region of the first line and the second line, the first memory cell including a first selection element layer and a first electrode coupled to the first selection element layer; and a second memory cell disposed between the second line and the third line at an intersection region of the second line and third second line, the second memory cell including a second selection element layer and a second electrode coupled to the second selection element layer. A threshold voltage of the first selection element layer is greater than a threshold voltage of the second selection element layer, and a resistance of the second electrode is greater than a resistance of the first electrode.

Abstract: The present invention relates to an oilfield management system. The oilfield management system comprises: one or more devices for measuring working conditions of oil wells, the one or more devices for measuring working conditions of oil wells are installed on one or more oil wells respectively for measuring working conditions of the one or more oil wells, the working conditions of oil wells at least comprise indicator diagrams of oil wells; one or more remote transmission units, each of the remote transmission units receives the working conditions measured by one or more of the devices for measuring working conditions of oil wells; and server, which determines running status of the one or more oil wells according to the working conditions of oil wells from the one or more remote transmission units; maintenance staff or administrators manage the one or more oil wells according to the running status of the one or more oil wells.

Abstract: Disclosed is a power management integrated circuit including dual one-time programmable memory banks and methods for controlling the same. In one embodiment, the power management integrated circuit (PMIC) includes a first one-time programmable (OTP) memory bank; a second OTP memory bank; and access control logic, communicatively coupled to the first OTP bank and the second OTP bank, the access control logic configured to: utilize the first OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is empty, write data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty, and utilize the second OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is not empty.

Abstract: Provided is a spin current magnetization rotational element including: a first ferromagnetic metal layer for a magnetization direction to be changed; and a spin-orbit torque wiring. The spin-orbit torque wiring has a structure in which a spin conduction layer and an interfacial spin generation layer are alternately laminated in the first direction, the number of a plurality of the interfacial spin generation layers is two or greater, and in the spin-orbit torque wiring, one of the plurality of interfacial spin generation layers is closest to the first ferromagnetic metal layer.

Abstract: Methods of operating a memory include activating a respective memory cell of each string of series-connected memory cells of a plurality of strings of series-connected memory cells, selectively activating a target memory cell of a selected string of series-connected memory cells of the plurality of strings of series-connected memory cells depending upon its data state, and deactivating a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells.

Abstract: A dynamic power control system includes an external power input terminal receiving a first output electric current from a power management circuit outside of the memory device; a variable charge pump receiving a second input voltage and a second input electric current, boosting the second input voltage to a second output voltage, and outputting the second output voltage and a second output electric current to the memory device; and a feedback controller to compare a ratio of the first output electric current to the first input electric current and a ratio of the second output electric current to the second input electric current, and to select one of the power management circuit and the variable charge pump to supply power to the memory device, according to the comparison result.

Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.

Abstract: Methods, systems, and devices that supports dual-mode modulation in the context of memory access are described. A system may include a memory array coupled with a buffer, and a multiplexer may be coupled with the buffer, where the multiplexer may be configured to output a bit pair representative of data stored within the memory array. The multiplexer may also be coupled with a driver, where the driver may be configured to generate a symbol representative of the bit pair that is output by the multiplexer.

Abstract: A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar.

Abstract: A method for writing memory cells including: applying a program voltage to a target wordline; grounding bitlines of memory cells to be written to a first resistance state; setting a bitline voltage of unselected bitlines; and setting a wordline voltage of unselected wordlines; applying the program voltage to a target bitline; grounding wordlines of the memory cells to be written to a second resistance state; setting the wordline voltage of the unselected wordlines to a first value if a peak of a maximum voltage drop is greater than or equal to a second value; otherwise, setting the wordline voltage to zero; and setting the bitline voltage of the unselected bitlines to a third value if the peak of the maximum voltage drop is greater than or equal to the second value; otherwise, setting the bitline voltage to zero.

Abstract: A method uses data retention time (DRT) characteristics of a logic-compatible gain-cell embedded DRAM (dynamic random-access memory) (GC-eDRAM) array in a transistor circuit as a source for physical unclonable function (PUF) signature extraction of the circuit.

Abstract: The present invention is directed to a method for programming a memory cell that includes a transistor and a memory element coupled in series between a first conductive line and a second conductive line. The method includes the steps of applying a voltage across the memory cell with the voltage being sufficiently high to enable switching of the memory element from initial resistance state to target resistance state; determining the initial resistance state of the memory element; comparing the initial resistance state with the target resistance state; and if the initial resistance state and the target resistance state are same, concluding that the memory element is already in the target resistance state and terminating programming process; otherwise, continually monitoring the voltage until a change in the voltage is detected and then concluding that the memory element has switched to the target resistance state and terminating the programming process.

Abstract: Some embodiments include an integrated assembly having a conductive line supported by a deck and extending along a longitudinal direction. The conductive line is configured to carry an electrical signal. A connection region is along the conductive line. The conductive line splits amongst multiple components as it passes through the connection region. The components are spread-apart from one another along a lateral direction which is orthogonal to the longitudinal direction. An opening extends vertically through the deck and through the connection region. The opening breaks one of the components of the conductive line to leave another of the components to carry the electrical signal across the connection region.

Abstract: Discussed herein are systems and methods for charging a bit line (BL) during programming of non-volatile memory cells. An embodiment of a memory device comprises a group of memory cells including a first memory cell coupled to a first BL and a second memory cell coupled to a second BL, and a BL charging circuit that provides an inhibit signal to the second BL in response to a control signal to program the first memory cell. To provide the inhibit signal, the BL charging circuit apply a supply voltage to the second BL for an initial wait time and, after the initial wait time, apply a higher voltage than the supply voltage, until the inhibit signal reaches a value of the supply voltage. The first memory cells is programmed in response to the established voltage on the second BL.

Abstract: Described herein is a non-volatile memory device in which it is possible to switch between different reading modes. In particular, the memory device includes a plurality of memory cells and implements, alternatively, a reading of a differential type and a reading of a single-ended type. Further described herein is a method for reading the memory device.

Abstract: Systems, methods, and apparatuses for temperature-compensated operation of electronic devices are described. For example, an apparatus for performing voltage compensation on a sense amplifier based on temperature may include a sense amplifier control circuit coupled to the sense amplifier to provide a compensation pulse to the sense amplifier, wherein the sense amplifier operates in a voltage compensation phase during the compensation pulse. The apparatus may determine the compensation pulse responsive to a voltage compensation duration signal that is based on the operating temperature of the apparatus. The voltage compensation occurs when there is no activate command immediately before or immediately after so that compensation duration change do not happen during an activate command from the command decoder.

Abstract: Systems, methods, and computer-readable media are provided for determining whether a node in a network is a server or a client. In some examples, a system can collect, from one or more sensors that monitor at least part of data traffic being transmitted via a pair of nodes in a network, information of the data traffic. The system can analyze attributes of the data traffic such as timing, port magnitude, degree of communication, historical data, etc. Based on analysis results and a predetermined rule associated with the attributes, the system can determine which node of the pair of nodes is a client and which node is a server.