Patents Examined by James Kerveros
  • Patent number: 7076703
    Abstract: A method for a memory redundancy, including a memory array typically having a plurality of columns (e.g., bit lines) of memory cells, and identifying a particular (e.g., defective) column of the memory array and further defining a redundancy window by selecting a group of adjacent columns including the defective column. The number of columns in the group of selected columns may be equal to the number of columns in a redundancy array that is coupled to the memory array. The redundancy array is used for storing information that would have been otherwise stored in the memory cells in the redundancy window. The selected group includes at least one column on one side of the defective column and another column on the other side of the defective column. Typically, there will be multiple columns on each side of the defective column.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: July 11, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Binh Quang Le, Pau-Ling Chen
  • Patent number: 7047466
    Abstract: An apparatus and method for allowing for dynamic wordline repair in a clock running system in addition to allowing for programmable fuse support of combined Array Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) testing. The method makes use of programmable fuses which contain Level Sensitive Scan Design (LSSD) latches which also have a system port. The system port allows for simpler reading of the fuses as well as for the dynamic updates of the programmable fuses for wordline and other repairs.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: May 16, 2006
    Assignee: International Business Machines Corporation
    Inventors: Patrick J. Meaney, Timothy G. McNamara, Bryan L. Mechtly
  • Patent number: 7007209
    Abstract: A method for testing the upstream channel of a cable modem system, using a tester, which generates and transmits a known test pattern to the Cable Modem Termination System (CMTS). If there are errors in the packet resulting from the upstream channel, the CMTS discards the packet based on standard Internet Protocol. If there are no errors the packet is returned on the downstream channel to the tester. The tester counts all returned test packets received including test packets with errors resulting in the downstream. Packets with errors are not discarded, but are checked for a portion of the repeating test pattern and checked for the correct number of bits of a test packet. All packets determined to be test packets, including those with errors, are counted over a period of time and compared to the number of packets originally sent.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: February 28, 2006
    Inventor: Richard Charles Jaworski
  • Patent number: 6968485
    Abstract: Ground bounce measurement circuitry, integrated circuit packaging, memory circuit modules, circuit cards, and systems, and methods to form, assemble, and use them are provided. A circuit combination is disclosed which includes an integrated circuit and measurement circuit, constructed so that each may be supported by a single substrate, or enclosed within a single integrated circuit package. The integrated circuit includes a test domain having a test voltage, and a reference domain having a reference voltage. The measurement circuit is operatively connected to the reference domain and the test domain to measure the ground bounce voltage, which is the difference between the test voltage and the reference voltage. The measured value of the ground bounce voltage can then be acquired by a data acquisition system, or made immediately available for observation using instrumentation outside of the substrate or integrated circuit package environment.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: November 22, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Steve Van Kirk
  • Patent number: 6959410
    Abstract: In a header decompression apparatus 709, a header decompressor 703 refers to reference information stored in a reference information manager 707 to decompress a compressed header of a packet received by a packet receiver 704. An error detector 702 detects a CRC error in the packet with its header decompressed by the packet receiver 704, and outputs only a correct packet. A successive error counter 705 counts the number of successive errors detected by the error detector 702. A successive decompression success counter 706 counts the number of decompression successes that successively appear. By referring to these counted numbers, an update request unit 708 transmits an update request to a transmitting side as required. A reference information manager 707 manages the reference information for header decompression. With this structure, the header decompression apparatus can request update of the reference information based on the state of the error.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: October 25, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Hata, Akihiro Miyazaki, Koji Imura, Daiji Ido
  • Patent number: 6847215
    Abstract: An electronic circuit for detecting a change with respect to a quiescent condition, which includes an oscillation circuit including a first and a second oscillator circuit, each oscillator circuit includes an oscillator input terminal and an oscillator output terminal on which an oscillation signal is present. The oscillator input of the first oscillator circuit is coupled with the oscillator output of the second oscillator circuit, and the oscillator input of the second oscillator circuit is coupled with the output of the first oscillator circuit. A detection circuit includes a first and a second detection circuit, each circuit further includes a detection input terminal and a detection output terminal on which a detection signal is present, while the detection circuit is arranged for detecting a change between the oscillation signals of the two oscillator circuits as a result of an external influence.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: January 25, 2005
    Assignee: Allsym B.V.
    Inventor: Jan Goezinne
  • Patent number: 6836864
    Abstract: Methods of testing a digital frequency synthesizer (DFS) having a programmable multiplier M and divider D. The full set of tests (wherein every value of M and D is tested) is reduced to a smaller set of tests in which each M/D ratio is tested to a specified resolution. A resolution and minimum and maximum values for M, D, and M/D are specified. An array is allocated, each M/D ratio having a corresponding location in the array, up to the specified resolution. For each MD pair meeting the specified criteria, an M/D ratio is calculated and idealized to the specified resolution, and the MD pair is stored in the corresponding array location. The result is an array of MD pairs that includes zero or one MD pair for each M/D ratio. Thus, by testing each MD pair within the array, all permissible permutations of the input clock frequency are tested.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: December 28, 2004
    Assignee: Xilinx, Inc.
    Inventor: Yiding Wu
  • Patent number: 6833714
    Abstract: A recording medium includes a computer readable program for controlling a computer. The program comprises (a) code for calculating a current distribution by using a strength and phase of magnetic field measured from a measuring object; (b) code for calculating a first electric field strength at a measuring point from the current distribution; (c) code for calculating a second electric field strength at the measuring point by using a current distribution of a predetermined position on a part of the current distribution of the measuring object; and (d) code for calculating a ratio related to the first electric field strength in association with the second electric field strength.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: December 21, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kouichi Uesaka, Takashi Suga
  • Patent number: 6810498
    Abstract: The outputs of selectors 230 to 23N are respectively connected to the data inputs DI0 to DIN of a RAM 10A. One inputs of selectors 540 to 54N are respectively connected to the data outputs DO0 to DON of the RAM 10A, the other inputs are connected to corresponding outputs of the selectors 230 to 23N. The outputs of the selectors 540 to 54N are connected to data inputs D of respective scan flip-flops 520 to 52N. Not in a RAM test mode, data input lines 210 to 21N are selected by the selectors 230 to 23N to provide to the data inputs DI0 to DIN of the RAM 10A and to the scan flip-flops 520 to 52N through the selectors 540 to 54N, respectively.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: October 26, 2004
    Assignee: Fujitsu Limited
    Inventor: Ryuji Shimizu
  • Patent number: 6807644
    Abstract: A JTAG testing system including a JTAG test equipment and a device under test compatible with the JTAG configured to form a synchronous data transmission connection with one another for transferring test data through a transmission path placed between predetermined interfaces. An asynchronous connection can be used as the transmission path between the interfaces, whereby the test equipment and said device under test are provided with a transceiver on the transmission path side configured to arrange the test data to be sent from said interface into a mode appropriate for an asynchronous transmission path and correspondingly to arrange the test data to be received from the asynchronous transmission path into a synchronous mode required by said interface.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: October 19, 2004
    Assignee: Patria Advanced Solutions Oy
    Inventors: Ilkka Reis, Mikko Simonen
  • Patent number: 6799288
    Abstract: An method, apparatus and article of manufacture for detecting and correcting memory device failures includig detecting errors in data stored in a memory device from the data transacted with a processor, correcting the detected errors in the data transacted with the processor, tracking the detected errors in the memory device, determining when the memory device has failed based upon the tracked detected errors and resetting the memory device when the memory device fails testing, and further, identifying erroneous latch-ups detected soon after powering and correcting errors such that no erroneous data is transacted with the processor.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: September 28, 2004
    Assignee: The Boeing Company
    Inventors: Kirk K. Kohnen, Billy Fitzgibbons
  • Patent number: 6791339
    Abstract: An apparatus for contactless measurement of carrier concentration and mobility includes a microwave source, a circular waveguide for transmitting microwave radiation to a sample, such as a semiconductor wafer or panel for flat panel displays, at a measurement location, a first detector for detecting the forward microwave power, a second detector for detecting the microwave power reflected from the sample, and a third detector for detecting the Hall effect power. A circular waveguide, carrying only the TE11 mode, is terminated by the sample behind which a short is located. Perpendicular to the plane of the sample (and along the axis of the circular waveguide), a magnetic field is applied. In this configuration, a given incident TE11 wave will cause two reflected waves. One is the ordinary reflected wave in the same polarization as the incident one. A detector is provided to measure this reflected radiation. The other reflected wave is caused by the Hall effect.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: September 14, 2004
    Assignee: Lehighton Electronics, Inc.
    Inventors: Jerome C. Licini, Nikolai Eberhardt
  • Patent number: 6784667
    Abstract: A system and method for estimating the remaining life of a light bulb, which includes a device for determining cold filament resistance of the light bulb while the light bulb is in a non-operating mode, a comparison device for comparing the cold filament resistance of the light bulb to a reference near an end of its life filament resistance, and a device for displaying an indication of a life expectancy for the light bulb. The system may be integrated into a vehicle or may be portable.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: August 31, 2004
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Robert V. Belenger, Gennaro R. Lopriore
  • Patent number: 6781388
    Abstract: A sensor includes a substrate consisting essentially of a non-conductive material, a first electrode, and a second electrode disposed on a first surface of the substrate, wherein the first electrode includes a first major portion traversing a length of the substrate and a finger extending from the major portion, wherein the second electrode includes a second major portion traversing the length of the substrate and a finger extending from the second major portion, wherein the first electrode finger extends toward the second electrode major portion and the second electrode finger extends toward the first electrode major portion and is substantially parallel to the first finger, and a third electrode connected to a ground, wherein the third electrode is interposed between and about the first and second electrodes.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: August 24, 2004
    Assignee: Delphi Technologies, Inc.
    Inventors: Da Yu Wang, Ying Jie Lin, David K. Lambert
  • Patent number: 6777921
    Abstract: An analog filter in an integrated circuit is tested by placing the filter in a feedback loop. The filter is tested by determining whether the analog filter, while in the feedback loop, provides a signal that oscillates within a predetermined tolerance of an expected frequency.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: August 17, 2004
    Assignee: Intel Corporation
    Inventors: Salem Abdennadher, Hassan Ihs
  • Patent number: 6777960
    Abstract: A method of inferring the existence of light by means of a measurement of the electrical characteristics of a nanotube bound to a dye first of all involves bringing a nanotube derivatized with a dye into contact with two conductor tracks. An electrical parameter of the nanotube is then measured via the two conductor tracks without exposure to light. Then the dye bound to the nanotube is irradiated, and the electrical parameter of the nanotube is then measured via the two conductor tracks with exposure to light. The difference between the value of the electrical parameter measured without exposure to light and the corresponding parameter measured with exposure to light is then established. Finally it is inferred, as a function of the difference established, whether light is present.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: August 17, 2004
    Assignee: Infineon Technologies AG
    Inventor: Eugen Unger
  • Patent number: 6774650
    Abstract: A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: August 10, 2004
    Assignee: Fujitsu Limited
    Inventors: Shigeyuki Maruyama, Daisuke Koizumi, Naoyuki Watanabe, Yoshito Konno, Eiji Yoshida, Toshiyuki Honda, Toshimi Kawahara, Kenichi Nagashige
  • Patent number: 6771057
    Abstract: In a circuit arrangement and method for testing a radio receiving system, the circuit arrangement includes multiple antennas, an antenna selector switch for the antennas, a receiver, and a diversity processor that controls the antenna selector switch. A diagnostic processor has an output terminal connected to a control input of the diversity processor, which provides at its output terminal, a signal that prevents the diversity processor from performing any further switching operations.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: August 3, 2004
    Assignee: Robert Bosch GmbH
    Inventor: Hans-Joachim Raddant
  • Patent number: 6763323
    Abstract: A spectrum analyzer comprises a mixer, which mixes complex conjugate input signal v*(t) into a base band signal x(t) and a resolution filter, which filters the base band signal for narrow band. In accordance with two aspects of the invention, the resolution filter has either a complex pulse response hused(t)=C1·e−C2·t2·e−j·C3·t2 or a real pulse response hused(t)=C4·e−C5·t2, in which C1, C2, C3, C4 and C5 are constants.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: July 13, 2004
    Assignee: Rohde & Schwarz GmbH & Co KG
    Inventor: Kurt Schmidt
  • Patent number: 6756801
    Abstract: According to one aspect of the invention apparatus is provided for electrical testing of a substrate having a plurality of terminals. The apparatus includes a frame, a probe card, a translation device, an alignment device, and a holder. The probe card includes a probe card backing member and a plurality of probes extending from the probe card backing member and is secured to the frame. The translation device is secured to the frame. The alignment device is located on the translation device. The holder is capable of holding a substrate and is secured to the alignment device. The alignment device is operable to cause alignment movement of the holder past the probe card so that selected ones of the terminals are brought into alignment with selected ones of the probes. The translation device is operable to cause translational movement, transverse to the alignment movement, of the alignment device with the holder towards the probe card.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: June 29, 2004
    Assignee: Electroglas, Inc.
    Inventor: Paul C. Colby