Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a shaped platform with a conductive post; mounting the shaped platform with the conductive post over a temporary carrier; mounting an integrated circuit device over the temporary carrier; encapsulating the conductive post and the integrated circuit device; removing a portion of the shaped platform isolating the conductive post; and removing the temporary carrier.

Abstract: Disclosed herein are intermediate and solder bump structures. In one embodiment, a structure comprises a primary solder column comprising primary solder material and configured to electrically contact a bonding pad on a semiconductor substrate. The structure also comprises at least one secondary solder column comprising secondary solder material in electrical contact with the primary solder column, the at least one secondary column having a height and volume less than a height and volume of the primary solder column. In such structures, the primary solder column is further configured to form a primary solder bump comprising the primary solder material and at least a portion of the secondary solder material through cohesion from the at least one secondary solder column when the intermediate structure undergoes a reflow process.

Abstract: The invention relates to a semiconductor device with a semiconductor chip and a rewiring layer, the semiconductor chip being embedded in a housing plastics composition by its rear side contact. The active top side of the semiconductor chip forms a coplanar overall top side with the top side of the housing plastics composition. The rear side contact is led to the overall top side via a flat conductor sheet tape, so that the rear side contact of the semiconductor chip can be accessed from the overall top side.

Abstract: The invention provides a semiconductor device with a bonding pad made of a wiring layer including aluminum and its manufacturing method that enhance the yield of the semiconductor device. The method of manufacturing the semiconductor device of the invention includes removing a portion of an antireflection layer (e.g. made of a titanium alloy) formed on an uppermost second wiring layer (e.g. made of aluminum) on a semiconductor substrate by etching, forming a passivation layer covering the antireflection layer and a portion of the second wiring layer where the antireflection layer is not formed and having an opening exposing the other portion of the second wiring layer, and dividing the semiconductor substrate into a plurality of semiconductor dice by dicing.

Abstract: Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.

Abstract: An integrated circuit structure comprising an air gap and methods for forming the same are provided. The integrated circuit structure includes a conductive line; a self-aligned dielectric layer on a sidewall of the conductive line; an air-gap horizontally adjoining the self-aligned dielectric layer; a low-k dielectric layer horizontally adjoining the air-gap; and a dielectric layer on the air-gap and the low-k dielectric layer.

Abstract: A low-cost and efficient process produces self-aligned vias in dielectric polymer films that provides electrical connection between a top conductor and a bottom conductor. The process is achieved by printing conductive posts on the first patterned conductive layer, followed by the deposition of an unpatterned layer dielectric, followed by the deposition of a second patterned conductive layer. The vias are formed during the flash annealing of the post after the dielectric is deposited, but before the second conductive layer is deposited. In this process, the post material is annealed with a flash of light, resulting in a release of energy which removes the dielectric on the top of the post.

Abstract: An airtight apparatus includes a package and a lid. The lid is bonded to the package and defines an airtight space, together with the package. The lid includes an optical window which allows the passage of optical signals, a holding part which holds the optical window, and a deformable part which is formed on an outer circumferential edge of the holding part and which is able to deform when applied with a load smaller than a load that deforms the holding part.

Abstract: A method for packaging a semiconductor device includes following steps. First, a first substrate including at least one first pattern is provided. At least one semiconductor device is disposed on the surface of the first substrate. Next, a spacer with at least one aperture and at least one through hole is provided. Then, the first pattern is aimed at the through hole to connect the first substrate and the spacer, so that the semiconductor device is positioned correspondingly to the aperture. Afterwards, a second substrate including at least one second pattern is provided. Thereon, the second pattern is aimed at the through hole, so that the second substrate is connected to the spacer correspondingly.

Abstract: There are provided a scribing step of performing scribing in a state in which a protective material is applied on at least one surface of a brittle material substrate, and a first scribing device that performs this scribing step. Accordingly, it is possible to form a vertical crack that reaches deep inside of the substrate, while effectively removing cullets produced at the time of severing the substrate, thus performing precise severing along a scribe line.

Abstract: An adhesive composition having thermal conductivity as well as excellent dispensability properties is provided. The adhesive composition includes a curable resin component, a curing agent for the curable resin component, and a conductive filler material. The filler material is an alloy of copper and silver. The specific ratios of the copper and silver in the alloy are tailored so as to provide the adhesive composition with appropriate thermal conductivity and dispensing properties making the composition particularly useful for application in the semiconductor industry.

Abstract: An integrated heat spreader, heat sink or heat pipe with pre-attached phase change thermal interface material and a method of making an electronic assembly.

Abstract: Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 ?m. The reason is as follows. If the diameter of the mesh hole is less than 75 ?m, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 ?m, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 ?m. The reason is as follows. If the distance is less than 100 ?m, the solid layer cannot function. If the distance exceeds 2000 ?m, the deterioration of the insulating properties of the interlayer resin insulating film occurs.

Abstract: The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing micro-channels or micro-trenches, and a technique for fabricating the same.

Abstract: A method of forming a small pitch pattern using double spacers is provided. A material layer and first hard masks are used and characterized by a line pattern having a smaller line width than a separation distance between adjacent mask elements. A first spacer layer covering sidewall portions of the first hard mask and a second spacer layer are formed, and spacer-etched, thereby forming a spacer pattern-shaped second hard mask on sidewall portions of the first hard mask. A portion of the first spacer layer between the first hard mask and the second hard mask is selectively removed. The material layer is selectively etched using the first and second hard masks as etch masks, thereby forming the small pitch pattern.

Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

Abstract: A method for forming through-wafer interconnects (TWI) in a substrate. Blind holes are formed from a surface, sidewalls thereof are passivated and coated with a conductive material. A vent hole is then formed from the opposite surface to intersect the blind hole. The blind hole is solder filled, followed by back thinning of the vent hole portion of the wafer to a final substrate thickness to expose the solder and conductive material at both the active surface and the thinned back side. A metal layer having a glass transition temperature greater than that of the solder may be plated to form a dam structure covering one or both ends of the TWI. Intermediate structures of semiconductor devices, semiconductor devices and systems are also disclosed.

Abstract: This invention relates to a semiconductor having protruding contacts comprising, a first semiconductor substrate having at least one interconnect located substantially within the first substrate, and a second semiconductor substrate having at least one protruding contact point that substantially contacts at least one interconnect.

Abstract: A method of forming flip chip bumps includes forming a plurality of metallization pads on a die. In another step, a structured layer having pores is formed on the die and metallization pads where the pads on the die are exposed through the pores. In yet another step, the die is transferred to a chamber having a liquid metal bath. In another step, a first pressure is created within the chamber followed by dipping the die in the liquid metal bath. In another step, a second pressure is created within the chamber such that liquid metal fills portions of the pores thereby forming metal pillars connected to the pads.