Abstract: An apparatus, method, and system for providing a stress absorption layer for integrated circuits includes a stiffening layer adapted to limit flexing. A compliance layer is physically associated with the stiffening layer, with the compliance layer adapted to absorb stress caused by mismatched thermal properties between two materials. A thru hole passes through both the stiffening layer and the compliance layer, with the thru hole being adapted to receive a solder joint. The stress absorption layer contacts both a semiconductor package and a substrate. The solder joint disposed in the thru hole connects the semiconductor package to the substrate.

Abstract: A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.

Abstract: A method of repairing a defective one of devices mounted on substrate is provided. Devices are arrayed on a substrate and electrically connected to wiring lines connected to a drive circuit, to be thus mounted on the substrate. The devices mounted on the substrate are then subjected to an emission test. If a defective device is detected in this test, a repair device is mounted at a position corresponding to a position of the defective device. At this time, after wiring lines connected to the defective device are cut off, the repair device is electrically connected to portions of the wiring lines, the portions of the wiring lines being located at positions nearer to the drive circuit side than the cut-off positions of the wiring lines.

Abstract: A method for internal electrical insulation of a substrate for a power semiconductor module having a framelike insulating housing with a cap and having an insulating substrate. The substrate has conductor tracks and power semiconductor components mounted thereon. The power semiconductor components are connected to connection elements, e.g., further conductor tracks or power semiconductor components, by means of bond connections. The method is characterized by the following steps: a) forming the substrate; b) coating the substrate with a viscous dielectric insulation compound in a casting process or immersion process; c) initiating the cross-linking of the insulation compound; d) with the substrate in a suspended position, permitting excess insulation compound to drip off, and securely enveloping the bond connections with insulation compound; and e) placing the substrate in the housing.

Abstract: An apparatus includes a metallization region including a plurality of metal layers on a device layer of a substrate, a via extending through the substrate and the device layer, and a heat spreading and stress engineering region in the substrate and adjacent to the device layer. The via contacts a metal layer in the metallization region.

Abstract: An integrated circuit includes a first die and a second die positioned in a package. The first die has a redistribution layer formed on the die and including a plurality of relocated bond pads. The relocated bond pads are positioned near an inner edge of the first die that is adjacent to an inner edge of the second die. Each relocated bond pad is coupled to a corresponding bond pad on the second die through a respective bonding wire. The first die further includes a plurality of original bond pads. The redistribution layer further includes at least one intermediate bond pad electrically interconnected through a respective conductive trace to a corresponding original bond pad. Each intermediate bond pad is electrically connected to a corresponding relocated bond pad through a respective bond wire.

Abstract: A film forming method comprising forming a liquid coating film on a substrate by supplying a liquid containing a coating type thin film forming substance and a solvent onto the substrate, substantially converging a variation in film thickness of the coating film, making the coating film stand by in an atmosphere including moisture under a predetermined condition after the substantial-convergence, the predetermined condition being such that a product of a time for which the coating film is exposed to the atmosphere and a water content per unit volume in an atmosphere in the vicinity of a surface of the coating film is made to be greater than or equal to a predetermined value, and forming a solid thin film on the substrate after the stand-by, the thin film being formed by carrying out an elimination of the solvent in the coating film and heat treatment for generating an irreversible reaction to the coating type thin film forming substance in the coating film.

Abstract: Processes for sealing porous low k dielectric film generally comprises exposing the porous surface of the porous low k dielectric film to ultraviolet (UV) radiation at intensities, times, wavelengths and in an atmosphere effective to seal the porous dielectric surface by means of carbonization, oxidation, and/or film densification. The surface of the surface of the porous low k material is sealed to a depth less than or equal to about 20 nanometers, wherein the surface is substantially free of pores after the UV exposure.

Abstract: In a method for fabricating a semiconductor device, interconnect grooves are formed in an insulating film on a substrate, and then a copper film is formed on the insulating film to fill the interconnect grooves. Subsequently, portions of the copper film existing outside the interconnect grooves are polished to form interconnects, and then a cleaning process is performed on the resulting substrate. Thereafter, moisture remaining around a portion of the insulating film exposed between the interconnects is removed in a vacuum.

Abstract: A circuit board having heating elements and a hermetically sealed multi-chip package. The multi-chip package includes a plurality of semiconductor chips, a substrate electrically coupled to the plurality of semiconductor chips, heat dissipation means, and a plurality of thermal interfaces disposed between the semiconductor chips and the heat dissipation means. The heat dissipation means forms a hermetically sealed cavity that encloses the semiconductor chips and at least a portion of the substrate. The circuit board includes a chip mounting surface, a chip mounting area on the chip mounting surface, the chip mounting area including a plurality of lands, and heating elements connected to the lands, the heating elements capable heating a joint formed between the lands and electrode pads of a semiconductor chip.

Abstract: A wafer processing method for dividing a wafer having function elements in area sectioned by dividing lines formed on the front surface in a lattice pattern into individual chips along the dividing lines, comprising a deteriorated layer forming step for forming a deteriorated layer on the side of the back surface of a position at a distance corresponding to the final thickness of the chip from the front surface of the wafer by applying a laser beam capable of passing through the wafer along the dividing lines from the back surface of the wafer; a dividing step for dividing the wafer into individual chips along the dividing lines by applying external force to the wafer in which the deteriorated layer has been formed along the dividing lines; and a back surface grinding step for grinding the back surface of the wafer divided into individual chips to the final thickness of the chip.

Abstract: Processes for sealing porous low k dielectric film generally comprises exposing the porous surface of the porous low k dielectric film to ultraviolet (UV) radiation at intensities, times, wavelengths and in an atmosphere effective to seal the porous dielectric surface by means of carbonization, oxidation, and/or film densification. The surface of the surface of the porous low k material is sealed to a depth less than or equal to about 20 nanometers, wherein the surface is substantially free of pores after the UV exposure.

Abstract: The present invention provides a semiconductor device exhibiting an improved reliability. A semiconductor device comprises a semiconductor chip having an electrode on a surface thereof and a mounting substrate, and the electrode (aluminum electrode) of the semiconductor chip is coupled to the mounting substrate through a bump (solder bump 104). A plurality of diffusion barrier films (UBM 112) for preventing a diffusion of a material composing the bump is provided between the electrode and the bump, and the diffusion barrier film is formed to have a plurality of divided portions via spacings therebetween.

Abstract: A chip-scale or wafer-level-package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed-package, is provided. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.

Abstract: A bond pad for an electronic device such as an integrated circuit makes electrical connection to an underlying device via an interconnect layer. The bond pad has a first layer of a material that is aluminum and copper and a second layer, over the first layer, of a second material that is aluminum and is essentially free of copper. The second layer functions as a cap to the first layer for preventing copper in the first layer from being corroded by residual chemical elements. A wire such as a gold wire may be bonded to the second layer of the bond pad.

Abstract: A plurality of metal interconnects incorporating dielectric spacers and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers adjacent to neighboring metal interconnects are discontiguous from one another. In another embodiment, the dielectric spacers may provide a region upon which un-landed vias may effectively land.

Abstract: A method for producing many semiconductor chips, each having a semiconductor circuit disposed on the face thereof and a die bonding film stuck to the back thereof, from a semiconductor wafer in which many rectangular regions are defined on its face by streets arranged in a lattice pattern, and the semiconductor circuit is disposed in each of the rectangular regions.

Abstract: An element is formed on the major surface of a semiconductor wafer, and a groove is formed in the back surface of the semiconductor wafer along a dicing line or chip dividing line by a mechanical or chemical method. A modified layer is formed by irradiating the groove with a laser, and the semiconductor wafer is divided by using the modified layer as a starting point. The back surface of the semiconductor wafer is removed to at least the depth of the groove.

Abstract: A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.

Abstract: Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.