Patents Examined by James Peikari
  • Patent number: RE46749
    Abstract: A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: March 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Koji Hosono
  • Patent number: RE46920
    Abstract: According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data “0” and data “1” in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance middle at a level in between an admittance of a variable resistance element storing data “0” and an admittance of a variable resistance element storing data “1”, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: June 26, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Katsuyuki Fujita, Kenji Tsuchida
  • Patent number: RE46994
    Abstract: Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: August 14, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-gon Kim, Ki-tae Park, Yeong-taek Lee
  • Patent number: RE47227
    Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: February 5, 2019
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Takeshi Ohgami
  • Patent number: RE47381
    Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region and having the first conductivity type; and a gate positioned betw
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: May 7, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: RE47772
    Abstract: The present invention facilitates convenient and secure distribution of proprietary content. A present secure content enabled drive system and method permits flexible use of storage medium for both protected distribution of information and user definable storage use. In one embodiment, a computer readable storage medium includes an unprotected information portion, a protected information portion and a protection interface. The unprotected portion stores unprotected information. The protected content portion stores protected information. The protection interface protects information in the protected content portion from unauthorized access.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: December 17, 2019
    Assignee: Nvidia Corporation
    Inventors: Michael B. Diamond, Jonathan B. White, Piers J. Daniell
  • Patent number: RE47840
    Abstract: A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: February 4, 2020
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Yoshiro Riho
  • Patent number: RE47877
    Abstract: Exemplary embodiments relate to methods, systems, and storage mediums for managing content storage and selection activities. The method includes aggregating content from content providers and presenting the content to a content device. The method also includes monitoring consumption of storage space with respect to storage capacity in the content device, relocating content contained in the storage space of the content device when a predetermined condition is met, and providing access to relocated content. The relocation is operable for freeing up the storage space of the content device.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: February 25, 2020
    Assignee: Chanyu Holdings, LLC
    Inventors: Barbara J. Roden, Douglas A. Bulleit
  • Patent number: RE47900
    Abstract: The present invention provides circuits, systems, and methods for programming a floating gate. As described herein, a floating gate tunneling device is used with an analog comparison device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate or multiple floating gates.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: March 10, 2020
    Assignee: TRIUNE IP, LLC
    Inventors: Ross E Teggatz, Wayne T Chen, Brett Smith, Erick Blackall
  • Patent number: RE48127
    Abstract: According to one embodiment, an information processing apparatus includes a memory includes a buffer area, a first storage, a second storage and a driver. The buffer area is reserved in order to transfer data between the driver and a host system that requests for data writing and data reading. The driver is configured to write data into the second storage and read data from the second storage in units of predetermined blocks using the first storage as a cache for the second storage. The driver is further configured to reserve a cache area in the memory, between the buffer area and the first external storage, and between the buffer area and the second storage. The driver is further configured to manage the cache area in units of the predetermined blocks.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: July 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Takehiko Kurashige
  • Patent number: RE48129
    Abstract: An elastic wave device includes resonators having a piezoelectric substrate, a resonation unit formed on the piezoelectric substrate, and reflectors formed on respective sides of the resonation unit on the piezoelectric substrate, and bumps formed on the piezoelectric substrate. The resonators are configured such that two or more split resonators are connected in parallel, and a bump is formed in a region sandwiched between reflectors of the split resonators.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: July 28, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Takashi Matsuda, Kazunori Inoue, Michio Miura
  • Patent number: RE48194
    Abstract: Shareable links can be created to share content items and information pertaining to activity on those shareable links can be monitored and stored in an online content management service. Based on this activity information, predetermined actions can be executed. These actions can include sending notifications regarding link activity, disabling shareable links, and/or updating sharing limitations related to the shareable links. Using the activity information, popular shared content items can be identified and recommendations for sharing unshared content items can be provided to the user. Additionally, advertisements can be tailored to the relative popularity of the shared content items.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: September 1, 2020
    Assignee: Dropbox, Inc.
    Inventors: Ilya Fushman, Nils Peter Welinder
  • Patent number: RE48206
    Abstract: A method, a mobile device arid and a computer program product for acquiring GPS on a mobile device possessing GPS capability are disclosed. The method comprises the step of setting a current value of the period of the power-up phase of the GPS dependent upon adaptive predictions of when the GPS should be powered on to meet specifications on positioning accuracy and GPS acquisition time.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 15, 2020
    Inventor: Robert Anderson Malaney
  • Patent number: RE48222
    Abstract: A system and method for dynamic RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to configure a first subset of the storage devices for use in a first RAID layout, the first RAID layout including a first set of redundant data. The controller further configures a second subset of the storage devices for use in a second RAID layout, the second RAID layout including a second set of redundant data. Additionally, the controller configure an additional device not included in either the first subset or the second subset to store redundant data for both the first RAID layout and the second RAID layout.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: September 22, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: John Colgrove, John Hayes, Bo Hong, Ethan Miller
  • Patent number: RE48244
    Abstract: A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 6, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Koji Hosono
  • Patent number: RE48350
    Abstract: The invention relates to an assembly comprising a main device and an accessory, which can be connected by a safe connector and a safe detection method. According to the invention, the assembly comprises: —a main device (2), —an accessory (3) connectable to the main device (2), —the accessory (3) comprising an accessory connector (4) for mating with a device connector (5) of the main device (2), —the accessory connector (4) and the device connector (5) each comprising one or more supply contacts (7) for transmitting electric power from the main device (2) to the accessory (3), —the main device (2) comprising a detection device (9), which, if connecting the accessory (3) to the main device (2), receives complex accessory data stored by the accessory (3) and which by positive evaluation of the complex data enables applying a supply voltage at the one or more supply contacts (7) of the device connector (5).
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: December 8, 2020
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Marcus Schwenk, Alexander Dubielczyk
  • Patent number: RE48448
    Abstract: A system and method for dynamic RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to configure a first subset of the storage devices for use in a first RAID layout, the first RAID layout including a first set of redundant data. The controller further configures a second subset of the storage devices for use in a second RAID layout, the second RAID layout including a second set of redundant data. Additionally, when writing a stripe, the controller may select from any of the plurality of storage devices for one or more of the first RAID layout, the second RAID layout, and storage of redundant data by the additional logical device.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: February 23, 2021
    Assignee: PURE STORAGE, INC
    Inventors: John Colgrove, John Hayes, Bo Hong, Ethan Miller
  • Patent number: RE48496
    Abstract: An electronic apparatus controls a peripheral device by using a relay apparatus. The electronic apparatus includes an interface connected to the peripheral device; a communication unit that performs communication with the relay apparatus; a receiver that receives a control signal for controlling the electronic apparatus; and a controller that, when the control signal is received, performs an operation based on the control signal, and controls the communication unit to transmit information about the performed operation and information about the peripheral device to the relay apparatus in order to control the peripheral device to perform an operation that corresponds to the performed operation.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-young Lee, Sung-young Ji, Seung-dong Yu
  • Patent number: RE48497
    Abstract: In electronic equipment device 1, a limitation level on reading an access level to selectively control the ability to read data from a USB flash drive (storage device) 2 is set to a setting section by an access level setting unit 3 in advance. The USB flash drive 2 ascertains the setting at the setting section 3 access level when the USB flash drive is connected to the electronic equipment 1 and limits reading data based on the determined setting device. If the limitation access level does not match with the condition for permitting data read-out as determined in USB flash drive 2 permit the reading of data, the USB flash drive 2 prohibits the electronic equipment 1 device from reading out data from a memory 24 of the USB flash drive by removing an application of power from the external device to the memory. By executing the processing for limiting data read-out at the side of the USB flash drive 2, unauthorized leakage of data can easily be prevented.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: March 30, 2021
    Assignee: Seagate Technology LLC
    Inventor: Tatsuaki Amemura
  • Patent number: RE48574
    Abstract: Systems and methods for estimating a time to cool down or warm up a building zone from a temperature setback condition are provided. A described method includes determining, by a controller for the building zone, at least one of a cooling demand for the building zone and a heating demand for the building zone for a time period corresponding to the temperature setback condition. The method further includes estimating a return time using at least one of the cooling demand and the heating demand. The return time is the time to cool down or warm up the building zone from the temperature setback condition.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: June 1, 2021
    Assignee: Johnson Controls Technology Company
    Inventors: John E. Seem, John M. House