Patents Examined by James Peikari
  • Patent number: 7509463
    Abstract: An atomic compare and swap operation that can be implemented in processor system having a power processor element (PPE) and a synergistic processor element (SPE) that have different sized memory transfer capabilities. The PPE notifies an SPE to perform a compare and swap operation on an address in main memory. The address has a size less than or equal to a maximum memory transfer size for the SPE and greater than a maximum memory transfer size for the PPE. The SPE atomically performs the compare and swap operation and notifies the PPE of the success or failure of the compare and swap operation.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: March 24, 2009
    Assignee: Sony Computer Entertainment, Inc.
    Inventors: James E. Marr, John P. Bates
  • Patent number: 7496718
    Abstract: A method for copying information from a first storage subsystem to a second storage subsystem is disclosed. The first and second storage subsystems are provided in a data storage system. The method comprises transmitting first data block from the first storage subsystem to the second storage subsystem, the first storage subsystem being associated with a first host computer and the second storage subsystem being associated with a second host computer; and transmitting first attribute information from the first storage subsystem to the second storage subsystem without intervention from the first host computer.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: February 24, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Ohno, Kiichiro Urabe, Toshio Nakano, Hideo Tabuchi
  • Patent number: 7490200
    Abstract: A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a second cache directory to access the second cache array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In the illustrative embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. An address tag associated with a load request is transmitted from the processor core with a designated bit that associates the address tag with only one of the cache array slices whose corresponding directory determines whether the address tag matches a currently valid cache entry.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: February 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Leo James Clark, James Stephen Fields, Jr., Guy Lynn Guthrie, William John Starke
  • Patent number: 7490206
    Abstract: A method (and structure) for relocating low memory for an operating system instance in a computer system includes establishing a low memory table (LMT), the LMT comprising information allocated for each of a predefined increment of the low memory to be relocated, setting the information to a first predetermined value, and copying a contents of each of the increments to a new location in a first copy operation.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: February 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Joefon Jann, Ramanjaneya Sarma Burugula, Pratap C. Pattnaik
  • Patent number: 7490215
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: February 10, 2009
    Assignee: Intel Corporation
    Inventors: Brent S. Baxter, Prashant Sethi, Clifford D. Hall, William H. Clifford
  • Patent number: 7490212
    Abstract: Data is written to a hard disk drive using shingled writing principles, i.e., each data track is partially overwritten when an immediately contiguous data track is written. Two or more contiguous data tracks establish a band, and a band may store data from one and only one file, such as an AV file.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: February 10, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Prakash Kasiraj, Richard M. H. New, Jorge Campello de Souza, Mason Lamar Williams
  • Patent number: 7487228
    Abstract: A cluster file system is disclosed. A plurality of disk servers, operating as a single distributed disk server layer, are connected to the one or more physical disks. Each disk server stores metadata for each of the files. A plurality of lock servers, having one or more locks for each file and associated file system metadata operates as a single centralized distributed lock server to coordinate access to the files stored by the disk server layer. A plurality of asynchronous file servers, operating as a single distributed file server layer in response to a request for a file from a user program: (i) retrieves the requested file from the disk server layer and at least one lock, associated with the retrieved file, from the lock server, and (ii) retrieves metadata for at least one file that is related to the requested files, and at least one lock, for each file that has had its metadata retrieved.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: February 3, 2009
    Assignee: Red Hat, Inc.
    Inventors: Kenneth Preslan, Michael J. Declerck, Matthew O'Keefe
  • Patent number: 7480904
    Abstract: An optical disc drive includes a firmware memory, a buffer memory, and a system control chip. The system control chip includes a processor and a memory update controller. When the optical disc drive is under a normal mode, the memory update controller is in an idle state. The processor controls the optical disc drive to fetch an update firmware from an optical disc and store the update firmware into the buffer memory. When the optical disc drive is under a firmware update mode, the processor is in an idle state. The memory update controller fetches the update firmware from the buffer memory and stores the update firmware into the firmware memory without the processor executing an update routine code.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: January 20, 2009
    Assignee: Mediatek Incorporation
    Inventors: Chi-Chun Hsu, Wen-Yi Wu
  • Patent number: 7480781
    Abstract: We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory interface to manipulate data from at least two memory channels, each memory channel corresponding to a portion of a distributed memory, responsive to the predetermined memory access command. The memory interface includes a plurality of memory controllers coupled to the command bus, each memory controller being operable to control a corresponding memory channel responsive to the predetermined memory access command, and a push arbiter coupled to each memory controller. The push arbiter being is operable to merge and align data retrieved responsive to each split read align command.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: January 20, 2009
    Assignee: Intel Corporation
    Inventors: Rohit Natarajan, Sridhar Lakshmanamurthy, Chen-Chi Kuo
  • Patent number: 7480754
    Abstract: The queue execution mode is selected based on the unique tag that is assigned to the command. In one method embodiment a tag is assigned for each of several disc access commands sent by the host. Two or more queues are created, each having a queue execution mode. Which of the queues is assigned to the command depends on the command's tag. One device embodiment comprises a data storage disc, a memory, and a controller. The memory is configured to hold several pending commands for accessing the disc(s),each of the commands having a unique tag. The controller is configured to execute each queued command according to a mode that is determined base on the command's tag.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: January 20, 2009
    Assignee: Seagate Technology, LLC
    Inventors: Anthony L. Priborsky, Robert B. Wood
  • Patent number: 7478270
    Abstract: An information processing device and information processing method including a management table that includes three pages. A pair of first and second pages is alternately used as a valid page and an invalid page to secure the data. The valid page is copied to a third page. Even when the power is shut off in the process of updating the page, at the next start time, the status of the data writing operation when the power is shut off is determined based on the validity and stability of the pages. Therefore, the data is restored without any corruption of valid page by using a proper restoring method.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: January 13, 2009
    Assignee: Sony Corporation
    Inventors: Taro Kurita, Toshiharu Takemura
  • Patent number: 7475206
    Abstract: A method of selecting logical volumes that are the targets for data migration to equilibrate the load on a system, based on the accessing data of the physical drives and logical drives under the disk array controllers, without increasing the load of the disk array controller. An external manager communicates with two or more disk array controllers, gathers and manages the access data and the configuration data relating to the physical drives and logical volumes of each disk array controller, and prepares an optimum data migration instruction to equilibrate the access load.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: January 6, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Akira Murotani, Toshio Nakano, Akinobu Shimada
  • Patent number: 7475205
    Abstract: An automated data library system employing a plurality of cartridges, one or more cartridge storage slots and an inventory controller. Each cartridge includes a cartridge memory. The cartridge storage slot(s) is(are) physically configured to store the cartridges. The inventory controller is operable to generate an inventory of the cartridges as stored within the cartridge storage slot(s). A generation by the inventory controller of the inventory of the cartridges as stored within the cartridge storage slot(s) involves the inventory controller simultaneously accessing cartridge identification information on two or more cartridge memories, and generating the inventory including two or more cartridges corresponding to the cartridge identification information.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: January 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Michael P. McIntosh, Shawn M. Nave
  • Patent number: 7472235
    Abstract: A multi-interfaced memory device includes an array of memory cells having a first interface and a second interface. The first interface and the second interface share an address bus and a data bus. One of the interfaces may be a random access memory interface and the second interface may be a paged access interface.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventors: David Dressler, Sean Eilert
  • Patent number: 7472262
    Abstract: Methods and apparatus are disclosed to prefetch memory objects. An example method includes identifying program states associated with an executing program; associating memory profiles with respective ones of the program states; identifying at least one next probable state based on calculated entropy values; and prefetching memory objects associated with the at least one memory profile corresponding to the at least one next probable state.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventor: Mingqiu Sun
  • Patent number: RE46749
    Abstract: A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: March 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Koji Hosono
  • Patent number: RE46920
    Abstract: According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data “0” and data “1” in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance middle at a level in between an admittance of a variable resistance element storing data “0” and an admittance of a variable resistance element storing data “1”, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: June 26, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Katsuyuki Fujita, Kenji Tsuchida
  • Patent number: RE46994
    Abstract: Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: August 14, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-gon Kim, Ki-tae Park, Yeong-taek Lee
  • Patent number: RE47227
    Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: February 5, 2019
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Takeshi Ohgami
  • Patent number: RE47381
    Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region and having the first conductivity type; and a gate positioned betw
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: May 7, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja