Abstract: A DSP (Digital Signal Processing) architecture with a wide memory bandwidth and a memory mapping method thereof. The DSP architecture includes: a first communication port; first, second, and third memory devices, which are connected with the first communication port and are arranged in a first row direction of the DSP architecture; a fourth memory device, a calculation element, and a fifth memory device, which are arranged in a second row direction below a first row direction of the DSP architecture; and sixth, seventh, and eighth memory devices, which are connected with the first communication port and arranged in a third row direction of the DSP architecture, wherein the calculation element is connected with the first through the eight memory devices.

Abstract: A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.

Abstract: A method, system and computer program product for efficient storage of data for use by an application, including a set top box. The set top box including a physical memory, a bulk storage device, and a memory management unit (MMU) coupled between the application and the physical memory and the bulk storage device. The physical memory and the bulk storage device are configured to store the data. The MMU is configured to translate a virtual address provided by the application to a physical address used by one of the physical memory and the bulk storage device.

Abstract: The on-chip copy process is extended so that the data may be copied between two blocks that may be on different chips, different planes on the same chip, or the same plane of the same chip. More specifically, the methods described here provide a single data copying mechanism that allows data to be copied between any two locations in a memory system. An exemplary embodiment uses an EDO-type timing. According to another aspect, selected portions of the relocated data, such as chosen words in a transferred page, can be updated in the controller on the fly. In addition to transferring a data set directly from a read buffer of a source array to a write buffer of a destination array, the data set can concurrently be copied, if desired, into the controller where an error detection and correction operation can be performed on it.

Abstract: A distributed file system is disclosed. A plurality of disk servers, operating as a single distributed disk server layer, are connected to the one or more physical disks. Each disk server stores meta-data for each of the files. A plurality of lock servers, having one or more locks for each file operates as a single distributed lock server to coordinate access to the files stored by the disk server layer. A plurality of asynchronous file servers, operating as a single distributed file server layer in response to a request for a file from a user program: (i) retrieves the requested file from the disk server layer and at least one lock, associated with the retrieved file, from the lock server, and (ii) retrieves meta-data for at least one file that is related to the requested files, and at least one lock, for each file that has had its meta-data retrieved.

Abstract: A memory architecture for a disk drive system in which Synchronous Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an interface protocol for transmitting information between these two memory components are provided to improve performance of the system, as well as reduce pin count and cost. An integrated circuit memory includes a random-access memory. The random-access memory includes a first terminal for receiving selection information. The random-access memory includes a second terminal for selectively (i) receiving a command, or (ii) receiving or transmitting data in accordance with the selection information received by the first terminal.

Abstract: A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache memory includes a cache array and a cache directory of contents of the cache array. In response to the first cache memory detecting on an interconnect a broadcast operation that specifies a request address, the first cache memory determines from the operation a type of the operation and a coherency state associated with the request address. In response to determining the type and the coherency state, the first cache memory filters out the broadcast operation without accessing the cache directory.

Abstract: Methods and apparatuses for improving processor performance in a multi-processor system by optimizing accesses to memory. Processors can track the state of a memory such that the memory can be efficiently utilized in a multi-processor system including the ability to decode incoming snoop addresses from other processors, comparing them to contents of a memory tracking register(s), and updating tracking register(s) appropriately. Likewise, the transactions from other non-processor bus agents and/or bus mastering devices, such as a bus bridge, memory controller, Input/output (I/O), and graphics could also be tracked.

Abstract: A method, system, and computer program manager for a computing system memory in the operation of a computing process. At least one memory segment provides memory resources for the computing process. The memory segment includes a plurality of memory objects, each of the memory objects includes an equal number of bytes and has a predetermined order that associates the address of the memory object in the memory segment to the addresses of the remainder of the plurality of memory objects. A pointer identifies a first memory object from the plurality of memory objects. The first memory object occupies a first ordered position according to the predetermined order. The process allocates the first memory objects from the memory segment during the operation of the computing process. The pointer increments to a second memory object having a second ordered position relative to the first memory object.

Abstract: A technique for realizing a snapshot function is provided, which can reduce data transfer between a server system and a storage subsystem which is necessary during data copy operations between storage devices and reduce the degradation of data access performance of the storage device in operation. In a storage system, a command processed by a CPU of a storage subsystem includes a COPY and WRITE command for performing a data copy process and a data storage process in accordance with a predetermined sequence, and a server system issues the command to the storage subsystem. After receiving the command, the storage subsystem executes a data copy process from a first disk drive to a second disk drive, and subsequently executes a data storage process to the first disk drive, thereby keeping a snapshot of the data stored in the first disk drive.

Abstract: Alignment of clusters to pages is provided in a non-volatile memory system that receives data from a host in clusters and writes data to a memory array in units of a page. Alignment is implemented within each block using offsets in logical-to-physical mapping of data. Different blocks may have different offsets. When a host sends data with different cluster boundary locations, the data may be written with different offsets so that data maintains alignment.

Abstract: A state machine implemented controller is provided in which a logic core 20 is reconfigurable in response to state data held within a memory 22. Thus, on transition from one state to a next state the data held within the memory 22 is used to reconfigure the operation of the logic core 20. This enables a relatively compact logic core 20 to be used time and time again, thereby avoiding the need to individually define a logic core appropriate to each individual one of the states that the state machine can enter into. This results in a controller which is much more compact on an integrated circuit die than is the case with prior art controllers.

Abstract: A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a set of sub-pages that comprise a same large page. Then, the DMMU receives a request for the first sub-page and in response to such a request, the DMMU instructs a pre-fetch engine to pre-fetch at least the second sub-page if the number of detected sequential accesses equals or exceeds a predetermined value.

Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.

Abstract: A method and apparatus of dynamically storing critical data of a gaming machine by allocating and deallocating memory space in a gaming machine is disclosed. One or more embodiments describe downloading or removing a new game to a gaming machine such that all existing critical data in NV-RAM memory is left intact. In one embodiment, the invention discloses a method and apparatus for dynamically allocating and deallocating memory space to accommodate either permanent or temporary storage in an NV-RAM. A method and apparatus is provided to monitor available memory space and dynamically resize the memory in NV-RAM. In one embodiment, a method is disclosed for performing an integrity check of the NV-RAM and determining whether a critical data error has occurred. In one or more embodiments, methods of compacting and shifting contents of an NV-RAM are described to consolidate available memory space or to prevent unauthorized access of NV-RAM memory.

Abstract: An improved method and system for client-side caching that transparently caches suitable network files for offline use. A cache mechanism in a network redirector transparently intercepts requests to access server files, and if the requested file is locally cached, satisfies the request from the cache when possible. Otherwise the cache mechanism creates a local cache file and satisfies the request from the server, and also fills in a sparse cached file as reads for data in ranges that are missing in the cached file are requested and received from the server. A background process also fills in local files that are sparse, using the existing handle of already open server files, or opening, reading from and closing other server files. Security is also provided by maintaining security information received from the server for files that are in the cache, and using that security information to determine access to the file when offline.

Abstract: A method, system, and computer-readable medium for maintaining up-to-date, consistent backup copies of primary data that are immune to corruption even when security of the primary data is breached. Independent security domains are established for primary and secondary data, such that access to each security domain must be obtained independently of access to the other security domains. For example, a host computer system having access to data storage in the primary security domain does not have access to data storage in the secondary security domain, and vice versa. Changes to primary data are synchronously replicated over a tightly controlled replication link from primary data storage in the primary security domain to secondary data storage in the secondary security domain. A change to the data is completed in the primary security domain when an acknowledgement is received that the change to the data has been stored in secondary data storage.

Abstract: A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type.

Abstract: A cache memory system includes a cache memory having a plurality of entries associated with a plurality of information storage units. Each of the information storage units is configured to store part of the information stored in a main memory. Reference bit storage units store a use status of entry data for a certain period of time. A hit detection circuit is connected to the information storage units. The hit detection circuit generates a hit signal to each of the reference bit storage units when the entry data is determined to satisfy use conditions.

Abstract: A method and apparatus of dynamically storing critical data of a gaming machine by allocating and deallocating memory space in a gaming machine is disclosed. One or more embodiments describe downloading or removing a new game to a gaming machine such that all existing critical data in NV-RAM memory is left intact. In one embodiment, the invention discloses a method and apparatus for dynamically allocating and deallocating memory space to accommodate either permanent or temporary storage in an NV-RAM. A method and apparatus is provided to monitor available memory space and dynamically resize the memory in NV-RAM. In one embodiment, a method is disclosed for performing an integrity check of the NV-RAM and determining whether a critical data error has occurred. In one or more embodiments, methods of compacting and shifting contents of an NV-RAM are described to consolidate available memory space or to prevent unauthorized access of NV-RAM memory.