Abstract: A semiconductor memory comprises a plurality of first data lines, a plurality of word lines disposed in such a manner as to intersect the first data lines, dynamic memory cells respectively disposed at the intersections between the word lines and the first data lines and including MOS transistors, a second data line connected to the first data lines through a switching circuit, an amplifier circuit connected to the second data line for detecting a read signal, and a write circuit for applying a write signal. The amplifier circuit includes at least one bipolar transistor.

Abstract: An erasable programmable read only memory (EPROM) cell having a floating gate and a control gate where the floating gate and the control gate are deliberately offset or asymmetrical from the source/drain and drain/source regions in the substrate. During programming, the source region is the one spaced apart from the gates while the drain region is aligned thereto. This orientation produces high gate currents to provide faster programming. During a read operation the aligned region now becomes the source and the spaced apart region becomes the drain to provide high drain currents for fast access. The asymmetrical EPROM cells of the present invention may be readily made using conventional spacer technology.

Abstract: A logic circuit including a resonant-tunneling transistor having a superlattice containing at least one quantum well layer, and a constant current source operatively connected between a base and an emitter of the transistor and supplying a constant current to said base. The transistor has a differential negative-resistance characteristic with at least one resonant point in a relationship between a current flowing in the base and a voltage between the base and emitter, and having at least two stable base current values at both sides of the resonant point on the characteristic, defined by the changeable base.multidot.emitter voltage. By supplying the base.multidot.emitter voltage having an amplitude of at least two amplitudes corresponding to the stable base current values, the transistor holds data corresponding to the base.multidot.emitter voltage.

Abstract: For precise read-out operation at an improved speed, there is disclosed a semiconductor memory device fabricated on a semiconductor substrate of a first conductivity type and including a plurality of memory cells, each memory cell comprising (a) an insulating film covering a surface portion of the semiconductor substrate, (b) a gate electrode formed on the insulating film and located over a channel forming region in the surface portion of the semiconductor substrate, a channel being produced in the channel forming region when the memory cell is selected, (c) a first impurity region having a second conductivity type opposite to the first conductivity type and formed in the surface portion of the semiconductor substrate, the first impurity region being contiguous to the channel forming region or spaced apart from the channel forming region depending upon a bit of information stored therein, and (d) a second impurity region of the second conductivity type formed in the surface portion of the semiconductor substr

Abstract: A nonvolatile memory device includes first and second voltage lines whose potentials are selectively set, first and second gate control lines, first to third MOS transistors which are serially connected between the first and second voltage lines, the first and third MOS transistors having gates respectively connnected to the first and second gate control lines and the second MOS transistor having a gate set in an electrically floating conditions, first and second capacitors respectively connected between the gate of the second MOS transistor and the gates of the first and third MOS transistors, and third capacitor connected between the gate and drain of the second MOS transistor.

Abstract: A Bloch line memory device and a method of erasing information in which, for erasure of a Bloch line pair representative of one bit of information and located in one end portion of one stripe domain, the stripe domain is stretched by decreasing the intensity of a bias magnetic field, an erasure Bloch line pair having a rotation of magnetization opposite to that of the to-be-erased Bloch line pair is injected into the end portion of the stretched stripe domain by supplying a current pulse signal to a conductor arranged substantially perpendicualr to the lengthwise direction of the stripe domain, and the stretched stripe domain is shrinked by restoring the intensity of the bias magnetic field, so that the to-be-erased Bloch line pair is combined with the erasure Bloch line pair to cancel the former.

Abstract: Double complementary storage is provided for a single binary digit in a quad store cross-tie memory. A correlated double sampling signal processing system is used to increase data signal level and facilitate discrimination in cross-tie memories. A method is also provided for accomplishing write and read functions in a quad store cross-tie memory using only a single pulse for either function. A set of four memory elements, arranged in two row-aligned complementary pairs, stores a single data bit, and is under four column conductors for reading data, two row conductors, and a write conductor for writing data.

Abstract: A semiconductor memory of a Bi-CMOS construction is disclosed. The memory includes a plurality of cell blocks connected in common to a pair of main-bit lines. Each of the cell blocks includes a plurality of word lines, a pair of pre-bit lines, a plurality of memory cell each connected to one of the word lines and to the pre-bit lines, and a pair of bipolar transistors having the respective bases connected to the pre-bit lines and the respective collector-emitter current paths connected in series between the main-bit lines. One of the bipolar transistors is turned ON in response to data stored in a selected memory cell to discharge the associated main-bit line. The discharging of the pre-bit line and the main-bit line is thus carried out rapidly to increase data read operation speed.

Abstract: A random access thin film magnetic memory is provided. Individual memory elements, characterized by serrated edges, are separated by connecting regions. Each connecting region has a polygonal-shaped opening therein with a first pair of adjoining edges having a length longer than the lengths of the remaining adjoining edges. Each memory element may be independently addressed through overlying row and column conductors to either read or write data into the element, and may contain a logic "zero" or "one" determined by the state of the magnetic domain found in the element.

Abstract: A semiconductor memory device comprises a plurality of memory cells arranged in a plurality of rows and columns, a plurality of row decoders for selecting one row of the plurality of rows, spare memory cells arranged in one row and a spare decoder for selecting the spare memory cells arranged in the one row. Each of the row decoders comprises a link element which can be melted by a laser beam. A plurality of decoder state determining logical circuits are provided corresponding to the plurality of row decoders. If and when a defective memory cell exists of the memory cells arranged in one row corresponding to each of the row decoders, the link element in the row decoder is melted in advance. When the row decoder having the link element melted in advance is selected by address signals, a corresponding decoder state determining logical circuit generates an SEE signal. The spare decoder is selected in place of the row decoder by the SEE signal.

Abstract: In a magnetic bubble memory device in which a major line and minor loops are constituted by ion-implanted tracks, a gate is constituted having two functions, i.e., having a replicate function and a pseudo swap function using conductor patterns of two layers that overlap on both the major line and on the minor loops. By controlling the pulsed current supplied to the conductor patterns of the two layers, the replicate function divides the bubble in the minor loop into two bubbles, so that one of the bubbles is taken onto the major line and is propagated to the detector. The pseudo swap function annihilates the bubble in the minor loop, divides the bubble on the major line into two bubbles and introduces one of them into the minor loop, thereby to realize the same function as that of the conventional swap gate.

Abstract: The invention provides a semiconductor memory device including a semiconductor substrate of a first conductivity type, comprising, a gate insulating film on a channel region of the semiconductor substrate, a floating gate on the gate insulating film, a floating gate insulating film on the floating gate, a control gate on the floating gate insulating film, first and second impurity regions of a second conductivity type in the semiconductor substrate and being adjacent to the gate insulating film, a third impurity region of the second conductivity type more lightly doped than the first and second impurity regions, being adjacent to the channel region, and a fourth impurity region of the second conductivity type more highly doped than the third impurity region and more lightly doped then the first and second impurity regions in the surface region of the third impurity region.

Abstract: A data storage system comprises a plurality of bubble memory chips each having a major loop and minor loops. At least one of the minor loops of each chip is used to store bad loop data for its respective chip. A system controller controls operation of the bubble memory chips. The system controller includes a chip controller for controlling operation of the bubble memory chips and a random access memory for storing the bad loop data from all of the bubble memory chips, and for supplying bad loop data to the chip controller so that data is placed only on operative loops of the bubble memory chips. A data transfer bus is used for inputting and outputting data from the system controller to a host computer. The system includes a plurality of bubble memory cassettes, each cassette having a predetermined number. Control signals are provided to the bubble memory chips of bubble memory chips so that more than one bubble memory chip is used simultaneously.

Abstract: In a semiconductor memory device capable of nibble mode operation, the time period required from the time when CAS signal falls to the time when a data output buffer activating signal rises is made different at the time of a normal mode and at the time of a nibble mode, so that the time period required for reading out data in the nibble mode is reduced as compared with a conventional device.

Abstract: A defect detection circuit for detecting a defect of a memory cell, a counter for counting defects detected by the defect detect circuit, and a remediableness determination unit for determining whether a count of the counter allows remedy by a redundancy circuit, are provided in a tester for a semiconductor memory or on a memory chip having a redundancy circuit. When the count of the counter is the same as or smaller than the number of at least one of the auxiliary rows and columns of the redundancy circuit, the memory is determined to be "remediable." Otherwise, the memory is determined to be "unremediable." When the count of the counter exceeds the number of at least one of the auxiliary rows and columns of the redundancy circuit, the memory test is interrupted.

Abstract: A power down logic control circuit employing a diode and a capacitor to develop a voltage from a main power supply which normally holds a transistor in an "off" state. Upon disconnection of the main supply, the transistor switches "on" and activates a second transistor. Upon activation, the second transistor produces an inhibit signal to tri-state memory control circuitry and thereby preserve the memory data during transition to standby memory power provided by a lithium battery.

Abstract: A Bloch line memory device in which a stripe magnetic domain is formed within a magnetic film for holding magnetic bubble domains, and Bloch line pairs are stored as information carriers within a magnetic wall defining the magnetic domain. In order to write Bloch lines into the magnetic wall of the stripe magnetic domain, current is caused to flow through a single conductor which is so disposed as to cross the magnetic wall of the stripe magnetic domain. On this occasion, the current through the single conductor is so directed as to generate an in-plane field opposite in sense to magnetization within the magnetic wall of the stripe magnetic domain.

Abstract: A current metering circuit is configured as a single stage charge pump for limiting the current level applied to the tunneling regions of an integrated circuit, nonvolatile, floating gate memory cell. The current metering circuit includes a storage capacitor which has one plate pumped by a periodic signal. The other plate of the capacitor is charged from a voltage that is boot-strapped from the voltage that presently exists across the active tunneling region. More particularly, a high voltage is applied to the drain of a transistor whose gate is connected to the tunneling region. The source of this transistor is coupled to a plate of the storage capacitor. This source develops a voltage equal to the present voltage across the load less the turnon threshold of the transistor. When the periodic signal goes low, the storage capacitor is charged from the voltage appearing at the source of this transistor.

Abstract: Disclosed is an integrated circuit comprising an electrically erasable programmable memory, the cells of which comprise a transistor with floating gate which is series connected with an access transistor, wherein, in order to prevent deterioration in the information stored in the transistors with floating gates, due to an excessive read voltage being applied to the cell, the circuit has, firstly, an additional cell constituted like the other cells and programmed in a state where its transistor with floating gate cannot be made conductive, the gate and the source of the transistor with floating gate of the additional cell being grounded, the drain and the gate of the access transistor receiving the memory reading voltage, and, secondly, a threshold comparator connected to the drain of the floating gate transistor to compare the voltage on this drain with the reading voltage and to give a signal in the event of any abnormal drop in the voltage at the drain.

Abstract: A C-MOS address buffer for use in a semiconductor memory device is clocked by an inverted column address strobe signal .phi..sub.CAL of an external column address strobe signal CAS. The signal .phi..sub.CAL is supplied to the drain of a feedback transistor in a schmitt trigger and is reinverted to provide a signal corresponding to the address strobe signal CAS. This signal is coupled to the gate of a transistor which controls the application of a supply voltage to the schmitt trigger circuit. Invalid timing address signals between the address input signal Ai and the clock signal comprising the signal .phi..sub.CAL are thus prevented. Also sufficient address set up time and hold time are guaranteed.