Abstract: A magnetic solid state device, such as a magnetoresistive memory cell, includes first and second layers of magnetoresistive material. The first and second layers are separated by a third layer which prevents exchange coupling between the magnetic dipoles of the first and second layers. The first, second and third layers are formed as a strip. A fourth layer of a resistive material, such as nitrogen doped tantalum, overlies the first layer. The fourth layer includes spaced, raised portions over which electrically conductive material, such as TiW, may be formed on top of the raised portions.

Abstract: A cassette type magnetic bubble memory comprise a bubble memory device including a bubble memory chip and lead terminals; a connector having contacts for electrically connecting the bubble memory device to an outside unit; thin flexible printed substrates for electrically connecting the contacts of the connector to the lead terminals of the bubble memory device; and a cassette case for accommodating therein the bubble memory device, the connector, and the printed substrates. The cassette case has inner walls. Some parts of the inner walls are in contact with at least some parts of an outer face of the bubble memory device to retain the device in the cassette case so that the majority of the outer face of the device is spaced from the majority of the inner walls of the cassette case. The bubble memory device and the connector are arranged in displaced positions along a plane common to the longitudinal direction of insertion of the cassette case into a bubble memory control unit.

Abstract: A memory comprising apparatus for selecting redundant rows of memory cells wherein the addressing of a defective regular row of memory cells coupled to a first set of bit lines results in the selection of a redundant row of memory cells coupled to a second set of bit lines such that signal interference resulting from the simultaneous enablement of two word lines in the memory is avoided.

Abstract: A memory cell having a plurality of storage structures in a differential arrangement. Two multilayered magnetoresistive memory cells are placed in a bridge arrangement with two impedance devices. The memory cells have one bridge juncture in common. Switches are connected to at least two of the four bridge junctures to permit the writing or reading of the magnetic state of the storage cells. The bridge arrangement combined with the appropriate switching action allows for a near doubling of the magnitude of the output sense signal while reducing the noise component of such signal.

Abstract: In a vacuum, recording is conducted by exposing a solid surface to a neutral particle beam or an ion beam modulated with a recording signal and converged, thereby to locally develop a change in composition on the solid surface. Then, reproducing is conducted by exposing said solid surface to an electron beam, an ion beam or a neutral particle beam which has been converged, thereby to emit electrons from the solid surface, and detecting the emitted electrons to read out the change in composition. If necessary, erasing is conducted by exposing the solid surface to the same beam as used in reproducing, thereby to eliminate the change in composition.

Abstract: In a magnetic bubble memory having a first system of aligned ion-implanted patterns and a second system of aligned ion-implanted patterns, a swap gate having a transfer conductor for transferring a magnetic bubble from the second system to the first system, and an erase conductor for erasing the bubble to be replaced on the first system.

Abstract: A circuit arrangement comprising a matrix-shaped memory for variable delay digital signals comprises a selection device for selecting columns of the memory, the selection device being switchable between two selected neighboring columns into which a portion of an external delay time setting data word is supplied for the selection of the columns. A dynamic switching by way of a supplied control signal is provided for switching between two neighboring columns. A setting and control device receives the full external delay time setting data word supplied thereto and generates a reset signal for the memory and a control signal for the selection device, and is supplied with an external reset signal by way of a reset input to directly reset the setting and control device and to indirectly reset the memory. The memory comprises a data input by way of which the data signal to be delayed can be input. The selection device comprises a data output by way of which the delayed data signals can be output.

Abstract: An integrated circuit device having a memory. A plurality of identical versions of a given piece of data may be stored at different addresses in the memory, and portions thereof read out in time-division fashion through a reduced number of sense amplifiers and common signal lines to majority logic circuitry, so as to enhance reliability while at the same time reducing the amount of area required on an integrated circuit chip.

Abstract: A semiconductor memory is provided with automatic refresh means including a timer, a refresh counter and a refresh buffer each formed on a semiconductor chip mounted with an asynchronous memory, for automatically performing a periodic refresh operation on the basis of a basic clock signal which is generated in response to the detection of a logical change in the output of the refresh counter. The automatic refresh counter includes means for performing one of a read operation and a write operation which are based upon a regular address signal asynchronous with the periodic refresh operation, in preference to the periodic refresh operation.

Abstract: In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, column address to the RAM unit is also used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the shift register containing only the data bits of interest.

Abstract: Method of determining the conductance state of a non-volatile memory device switchable between high and low conductance states. The device comprises at least one p-type amorphous or microcrystalline semiconductor and an n or i-type layer. The device is irradiated with light to produce a photovoltaic response which is used to determine the conductance state.

Abstract: A magnetic bubble memory device comprises contiguous-disk ion-implanted magnetic bubble propagation tracks formed by implanting selectively ions in a magnetic layer which can hold magnetic bubbles. At least one of the disks which form the ion-implanted bubble tracks and each of which may have a circular or square shape, is configured to include a combination of arcs of circles having different curvatures or a combination of sides of squares having different sizes.

Abstract: A hybrid magnetic bubble memory device includes, magnetic bubble propagation tracks formed of partial ion-implantation and bubble propagation tracks formed of a soft magnetic material pattern. At least one of the junctions between the two type tracks is located on a corner soft magnetic material pattern where the bubble propagation direction is changed, and the hairpin conductor is superposed on the part of the corner pattern under which the magnetic material is not ion-implanted to form ion-implanted propagation tracks.

Abstract: A dynamic semiconductor memory device including memory cells divided into a plurality of blocks (1-1, 1-2). A simultaneous write enable circuit performs a write operation simultaneously upon the plurality of blocks, and a comparison circuit compares read data of one block with read data of the other block, thereby carrying out a test.

Abstract: A magnetic bubble memory device for implementing its high storage density for practical use is generally composed of ion-implanted elements occupying the most part of a minor loop, and other elements made of soft magnetic materials. The ion-implanted minor loop with a higher density is folded several times, and includes straight propagation tracks adjacent to each other and connected by an inside turn, with another straight propagation track having an outside turn facing the inside turn being placed between the adjacent straight tracks.

Abstract: An apparatus for reducing the write recovery time of a memory during a write operation is responsive to the detection of a write enable signal for causing the data being written into a selected memory cell to be immediately coupled out on the memory's corresponding output data line independent of the speed at which the data is actually written into the memory cell. The state of a cache memory element is set to reflect this data state such that when the write enable signal goes off, the cache memory element maintains the present state of said output data line. The cache memory element is overridden as the corresponding memory cell reaches a steady state condition at the end of the write operation.

Abstract: An integrated circuit device which includes a memory array comprising a plurality of respective memory locations for storing binary data, each respective memory location corresponding to a respective combination of binary address signals, the device further comprising: at least two respective ports for receiving respective combinations of binary address signals corresponding to respective locations of said memory array; transition detection and signal providing circuitry for detecting a change in a respective binary address signal combination received by either a first or second of the at least two ports and for providing a first transition signal in response to a change in a respective first combination of binary address signals received by the first port and for providing a second respective transition signal in response to a change in a respective second combination of binary address signals received by the second port; and contention detection and signal providing means for receiving the first and the sec

Abstract: An inhibit and transfer circuit for a memory system having multiple read ports. Bit lines are precharged. In a reading operation, the precharging is disconnected at the same time that the bit lines are selectively connected to one or more sense latches, associated with multiple reading ports. Feedback paths in the sense latches are disconnected during the reading. The selection of the sense latches to which the bit lines are coupled is determined by a comparison of multiple addressing signals.

Abstract: A semiconductor memory device which includes a high potential source, a low potential source, and a word line driver portion which makes the potential of selected word lines a selection level lower by a predetermined potential than the high potential source. Memory cells are connected to the word lines. A first low potential source or a second potential source is connected to the low potential source. A plurality of transistors are provided in the word line driver portion so as to connect a plurality of stages. When the memory has a sufficient power source margin, the word line driver is formed as a two-stage device so as enable high speed operation. When the memory has an unsufficient power source margin, the word line driver is formed as a one-stage device so as to ensure a sufficient power source margin.

Abstract: A memory circuit is divided into a plurality of memory blocks, and an address register and a delay register are disposed in each memory block. Therefore, a read or write operation and a shifting operation of the address for storing data inside a memory matrix can be realized by a pipeline technique, and hence a memory circuit having a high processing speed is obtained.