Abstract: A memory control processor adapted to expand a random access or accelerator memory by logical overlays which performs these overlays into memory fields (pages) on the basis of page usage history. To provide a quick reference to page use a chronological sequence is established by links rather than by reordering a stack. This link sequence is tied by very limited leads to the rest of the memory control processor and can therefore be updated during each memory access. In addition the memory control processor includes a task priority logic integrating various competing memory access requests with the overlay operations. To achieve the various transfer modes in the quickest time the memory control processor is organized around a wide control memory storing the tank servicing sequences. The width of the control memory and the associated task logic allow general purpose microprogrammable direct memory access which may further be utilized in multiplexed fashion to accommodate various concurrent tasks.

Abstract: A memory control processor adapted to expand a random access or accelerator memory by logical overlays which performs these overlays into memory fields (pages) on the basis of page usage history. To provide a quick reference to page use a chronological sequence is established by links rather than by reordering a stack. This link sequence is tied by very limited leads to the rest of the memory control processor and can therefore be updated during each memory access. In addition the memory control processor includes a task priority logic integrating various competing memory access requests with the overlay operations. To achieve the various transfer modes in the quickest time the memory control processor is organized around a wide control memory storing the task servicing sequences. The width of the control memory and the associated task logic allow general purpose microprogrammable direct memory access which may further be utilized in multiplexed fashion to accommodate various concurrent tasks.

Abstract: Two or more processors share a large main memory in which are stored the programs and data sets on which the processors operate. Each processor operates independently from every other one, and selects its tasks for operation on the basis of information contained in tables which may be updated independently by each processor.

Abstract: A video terminal system having a plurality of distinct output devices providing humanly perceivable, alphanumeric information is disclosed. The video terminal processes and transfers the binary representations of each alphanumeric character to a character generator. A dot matrix corresponding to the character is provided by the character generator and is time-multiplexed so as to be time-shared by each of the output devices without the requirement for specialized circuitry and with minimal time degradation. The distinct output devices may be video displays and hard copy printers which display alphanumeric characters for a complete line, the video display devices receiving each complete line of characters in a predetermined time period and the printer devices receiving a slice of each character for a line upon request.

Abstract: An interface for coupling a computer to a plurality of magnetic tape transports, including dual-density transports and combinations of high and low density transports. The interface includes an automatic density selector for detecting the density of data stored on a tape prior to reading and for storing this information for as long as the tape is being used. A read-only memory and other logic circuitry translate computer operating commands into commands readable by a transport formatter. The interface also couples digital data between the computer and the formatter and converts formatter status information into language readable by the computer.

Abstract: A data processing system is described which has multiple sets of registers each of which is capable of autonomously controlling a common storage and common arithmetic and logic control circuits to execute respective tasks of a program. Level status blocks (LSBs), each assigned to a respective task, are held in main storage; and each contains such address and status data as is required for task execution in a controlled environment.

Abstract: One of a series of hardware/firmware primitives is disclosed for converting a general purpose digital computer into a database machine. The invention comprises a hardware/firmware implemented machine instruction which determines the appropriate register where a database pointer is currently stored, retrieves the pointer from that register and then stores the pointer into main memory.

Abstract: Two of a series of hardware/firmware primitives are disclosed for converting a general purpose digital computer into a database machine. The invention comprises two hardware firmware implemented machine instructions which both fetch a set descriptor, which along with a base register BR, allow access to a record. For the Test Set Empty operation, the record accessed is an owner record and a check is made to see whether the set has any member records currently associated with it. For the Test Member Inserted operation, the record accessed is checked to see whether it is currently inserted as a member of a particular set (i.e., a part of that set).

Abstract: A host system includes a microprogrammed processing unit which couples a foreign processing unit to the main memory of the host system. The microprogrammed processing unit also couples to an interface connected to the foreign processor. During operation, the host processor transfers a channel command to the microprogrammed processing unit which is operative under firmware control to perform the various control functions required for initiating a particular job. In this manner, the various parameters and information necessary to dispatch a job of the foreign processor is accomplished expeditiously under the firmware control in response to commands issued by the host processor.

Abstract: A signal analyzer system is disclosed which includes an arithmetic processor containing a plurality of pipeline processor elements in parallel array with each element connected to a respective working store, with all of the elements being under microprogram control of an arithmetic element controller.A storage controller included in the system is connected to the arithmetic processor, to a system input and to a system ouput.A bulk storage included in the system is connected to the storage controller. The storage controller controls data transfers into and out of the system and between the bulk storage and arithmetic processor.A control processor included in the system is connected to the arithmetic processor and the storage controller by means of a data bus for centrally controlling the operation of the plurality of pipeline processor elements by transmitting micro control words over the bus.

Abstract: A data processing system, comprising a central unit, peripheral units, and input/output processors which are connected parallel to a common bus. The said processors centralize the exchanges between a plurality of peripheral units and the store. The data exchanges can be effected in the mode "programmed bus", in which the central unit is the master of the system, or by way of the "multiplex bus", where the exchange is controlled by the input/output processor in word blocks. The interruption system utilizes a second bus which is independent of the first bus, so that the simultaneous transfer of the interruption vectors and data is possible.

Abstract: Redundant but independently operable data processors called encoders are arranged so that control of a particular recorder gathering billing data in a telephone switching system can be transferred while maintaining billing continuity for calls being handled by that recorder. More specifically, each encoder checks the validity of billing information received from each recorder. However, each encoder only transmits billing data pertaining to a designated group of recorders to a remote processor. When an encoder detects that it is not receiving valid data from one of its designated recorders, the control of only that designated recorder is transferred to the other encoder if the other encoder indicates that it is receiving valid data from that recorder.

Abstract: An information-transmitting apparatus for transmitting data records, each comprised of a plurality of data words (column data items), each word comprising a plurality of digits, wherein data words of a data record are compared with the next successive record which is also comprised of a plurality of data words. Each data word of a first record is compared on a digit-by-digit basis with the corresponding data word of a second record, and various digits of the data words of the second record which are identical with those of the corresponding data words of the first record are omitted. Deletion of identical digits of a data word of a second record is continued until a non-coincidence detection signal is produced. Then, the remainder of the digits of the data word of the second record are transmitted. Additionally, special codes which separate the data words and which separate the records are also transmitted.

Abstract: A programmable interface controller capable of assuming specific sequential control functions is disclosed. The disclosed controller is a slave device under the direct control of the numerical control computer and is effectively transparent to numerical control machine system. Upon a first command the interface controller receives and stores data from the numerical control computer. The stored data is processed in accordance with an internal program and the results of the processing temporarily stored therein. Upon a second command, the results of the processing are returned to the numerical control computer from where they are distributed via the systems bi-directional bus to the machine as well as to operating routines elsewhere in the numerical control system.

Abstract: In an information processing system of the type having widely dispersed terminals tied together by a series communications link, common data which is of interest to all stations is collected and registered in a simplified manner. The common information, consisting of the status of each of the stations, is collected by any station sending out a search instruction as part of an information word. As the information word passes through each successive station, each respective station adds a status bit to the information word indicating the status thereof. When the new-completed information word returns to the originating station, the common data is registered and displayed. Also the common data is sent, along with a "register common data" instruction, to all other stations via the communication link. Upon receipt of such information and instruction, each station registers and displays the common data.

Abstract: An electronic computer comprising a first memory for recording instructions and data to be processed, a second memory for recording microinstructions and addressable by the instructions to provide a succession of microinstructions which is associated with each of the instructions and a third memory for recording a plurality of words and addressable by the microinstructions to provide at least one word associated with each of the microinstructions. Operation control means and a plurality of registers connectable to the control means and to the memories are provided for processing the data and two groups of signals are included in the words for controlling the operations of the control means and the registers. The control means and the registers are directly supplied with the signals of the first group for selecting the operations to be performed according to the signals of the first group.

Abstract: A data capture terminal is disclosed which is particularly applicable for two-way data communications with a remote facility, such as a central data processor. The terminal employs a memory for storing data entered into the memory from various peripherals, such as an information reader, or a manually operated keyboard, or an input/output peripheral, such as a central data processor. Data entered into the memory from one of these peripherals may be communicated to an output peripheral, such as a visual display or a printing mechanism, or to a remote facility.

Abstract: A printer responds to channel commands including coded data received over a channel from a data processing unit by printing characters represented by the coded data using an electrophotographic printing arrangement. The coded data received by the printer is first translated into corresponding graphic codes or addresses by a translate table employing a predetermined translation code, following which the addresses are used to locate sets of character image bits stored within a plurality of character generator modules. Each set of character image bits is used to modulate a laser scan of a printing drum to effect printing of desired characters. Both the translate table and the character generator modules are program alterable, and the data stored therein can be loaded directly from or changed in response to data and instructions from the data processing unit.

Abstract: This invention relates to a method and apparatus for processing yarn defect signals of a plurality of yarns on the on-line base.For this purpose and in the case of the signal processing apparatus according to this invention a large number of yarn defect signals are processed through a scanning device for signal sampling, means is provided for placing possible drop-out signals into respective provisional memories, and preferably in the form of a binary "1" from a binary "0" and for reading out the contents from the memories at the beginning the next succeeding sampling period and for further processing these read-out yarn defects signals, together with regular yarn defects signals under processing through regular samplings.

Abstract: A system for retrievably providing a video display of a pictorial information message on a video display device from video information stored, such as on a video tape, in a plurality of frames, unique pictorial information being stored in each frame for display thereof in response to a request therefor, the frames each including a plurality of segments with one displayable pictorial information message being contained in each segment, the selected segment being retrievable for individual display of only this requested pictorial information containing frame segment. The video tape storage media in addition to the video track upon which the pictorial information is stored, contains an audio track having unique frame identification code information stored thereon for providing a frame location signal which is utilized to retrieve the frame.