Abstract: A shift and rotate circuit is disclosed for a processor which receives 16-bit words as input data, which breaks down each received word into four 4-bit bytes, and which performs logical and arithmetic operations on each word on a byte-by-byte basis. A word is shifted a specified number of bit positions (1) by entering the word byte-by-byte in consecutive locations of a first 4-bit wide memory, (2) by entering the same word in an ordered byte sequence in a second 4-bit wide memory with the ordered sequence being determined by the number of bit positions the word is to be shifted, and (3) by concurrently applying the contents of both memories byte-by-byte to the shift and rotate circuit which shift the received information to the required number of bit positions and writes the shifted information into consecutive locations of the second memory. The 4-bit bytes of the shifted word are ultimately reconstituted into a 16-bit word and outputted onto the I/O system.

Abstract: The chip architecture of an MOS microprocessor chip includes data bus input-output buffer circuitry located along the lower right hand edge of the chip. High order address buffer output circuitry is located along the bottom of the chip. Directly to the left of the data bus input-output buffer circuitry is the arithmetic logic unit circuitry, and to the right of this and adjacent to the high order address bit buffer circuitry is located a register section including first accumulator register, a second accumulator register, high and low order index registers, a high order incrementer and an associated program counter, a low order incrementer and associated program counter, a high order stack pointer register and a low order stack pointer register, and a temporary register arranged on the surface of the microprocessor chip in a particular sequence. To the left of the register section and along the lower left hand edge of the chip is located a plurality of low order address bit buffer circuits.

Abstract: In a control unit having a read only memory, a control program is provided which has provision for all features with which the machine may be equipped and for a selected number of future features. The control program contains one or more mainline control loops which interrogate mainline and feature functions sequentially to determine whether a function requires service. If a function is present and requires service, the appropriate routine is executed whereafter the mainline control program proceeds to execute the next indicated control program instruction. If a function is present, but does not require service, a normal return or other procedure is executed to return to the control loop. When a feature is addressed which is not present, a feature return is executed forcing the control program back to the instruction following the last branch.

Abstract: A programmable sequence controller for controlling a machine or process operation including a main low-security programmed sequencer and a high-security programmed sequencer through which selected outputs from the main sequencer must pass before being allowed to control the machine or process operation. This high-security sequencer generates a sequence of steps which relate to machine or process commands under conditions critical to the operation of the machine or process and is controlled in a predetermined order. Any critical output requested by the main sequencer is caused to initiate sequencing by the high-security sequencer and is tested by the high-security sequencer as to the propriety of the generation of a permitted output to the machine or process. The high-security sequencer in this manner effects an improved interlocking between the various critical output commands and actual operative conditions.

Abstract: An improved microinstruction memory addressing method and apparatus within a serial-bit microinstruction processor incorporating internal, serial-byte transfer, is provided by addition to and alteration of memory control circuitry wherein the resulting permissible microinstruction set for controlling the processor may be expanded to include a CALL, GO-TO and EXECUTE operations, thus increasing the programmatic capabilities in the processor. The micro-code needed to define more complicated program operations, and thus the time used to perform these operations, may therefore be greatly reduced. Changes may also be made in existing timing circuitry.

Abstract: For a serial-bit, programmable microinstruction processor having serial-byte internal transfers, an expanded-memory addressing apparatus and method is provided by the incorporation into the processor system a plurality of external memory units and a selection and transfer circuitry for accessing external memory space from within the processor. The accessing of external memory locations may be controlled by programmed memory access command instructions. These instructions may be operated upon by decoding components and buffer storage components to make available, concurrently, the entire contents of a particular one of the external memory units. Once a particular memory, or page is selected, a location within that page may then be addressed by memory address registers within the base processor.

Abstract: A programmable automatic controller for operating machines having a plurality of components which operate in a timed or sequential relationship with one another. The controller includes a timing means for generating cycle clock pulses in synchronism with the operation of the machine, wherein the cycle clock pulses provide an instantaneous indication of the time elapsed in each cycle of operation of the machine. A COS/MOS running storage means stores the relative times during each cycle of machine operation when each of the plurality of machine components are to be enabled and/or inhibited. When the time elapsed in a cycle corresponds to a component actuating time stored in the running storage, an actuating signal is generated by a comparator. This signal is coupled to a machine component addressing arrangement which provides a component enable or inhibit command signal to the addressed component whose actuating time compared to the cycle time lapsed.

Abstract: A memory module containing addressable memory devices, and the circuits necessary to address and drive these devices, is configured so that a trade-off between memory size and word length can be made by rewiring the backplane. Thus, a single memory module design can be used for a variety of computer memory applications. This is accomplished by incorporating on the module a complete set of addressing and signal driving circuits, and allowing for the control of these module components through a system of control lines wired through the backplane.

Abstract: This invention is a new concept for the organization of digital data processing apparatus, suitable for highly parallel execution of certain computations involving repeated patterns of computational operations. Possible applications include many types of signal processing computations such as filtering, modulation and waveform generation. The invention permits exploitation of the unique properties of asynchronous digital logic.

Abstract: A data-processing system for pattern recognition and the like, having an instruction unit (IU) for storing, decoding and modifying instructions, and an execution unit (EU) for storing and performing operations on data. The IU has facilities for making a branch address effective for a plurality of subsequent instructions, and for masking and de-conditioning the prospective branch. The IU also indexes data-operand addresses according to a variable modulus. The EU performs Boolean and voting logic functions in a series of cascaded registers. The EU controls the acquisition of external data according to the type of instruction being executed, and maintains a record of the location of data strings in memory. Intermediate computational results are automatically placed in a hardware stack without any programming overhead. Bits from multiple operands are placed in a single operand byte by shift-load instructions.

Abstract: A branch-address translation register (BAXR) is loaded by a current or a prior control word field. A word selection decoder circuit receives the BAXR outputs and combines them with machine-status signals to generate a word selection signal for selecting a control word from a currently accessed branch group in the control store. A BAXR switching circuit is also provided so that any control word can switch off the BAXR output and cause a control word selection without translation. The invention can obtain any required degree of addressing flexibility in microcode branch selection, i.e. from partial to total flexibility.

Abstract: A host microprogrammed data processing system includes a plurality of tables to store information coded to define a plurality of a variety of different input-output system configurations of resources required to execute input-output instructions in a corresponding number of target systems being emulated by the host system. The host system further includes emulation apparatus which includes a control store which stores microprograms for directing the system in processing input-output instructions of target programs and for verifying whether each such instruction can be executed by the host system. The emulation apparatus generates coded information indicating which one of a given number of channel program routines the host system is required to use to execute the input-output instruction using the host input-output resources. Using the information of the tables, the emulation apparatus is able to execute completely certain types of target system input-output instructions used to perform control operations.

Abstract: A control unit controls a data processing system port to communicate with different peripheral devices. The control unit determines the type of peripheral device that is being serviced and whether the port apparatus is transmitting or receiving data, and accordingly, activates a program to load a particular count into a counter. Upon reaching a specified count, the counter activates the control unit to control the sampling time of the incoming signal and to determine the interval of time or frequency of the transmitted data information signals.

Abstract: A system is disclosed for controlling access to a central information processor by a plurality of peripheral devices. The system determines access on the basis of a (1) predetermined hierarchical priority order and (2) a cyclical scanning process. To achieve this, a system of hierarchically organized priority levels is combined with a system of cyclical scanning in a manner such that no single device may monopolize the central processor.

Abstract: A processor including a plurality of synchronized subprocessors, each implemented on an integrated circuit substrate and each having an instruction register and instruction executing circuits for independently executing a portion of the functions required by an instruction being simultaneously executed by each subprocessor. Execution is initiated and synchronized by simultaneously loading the same instruction into each subprocessor.

Abstract: A control device for n recording elements for data which are part of a given plurality of data which can be recorded by each of said elements.This device is made up of n identical control circuits connected respectively to the recording elements, each of said circuits including:-- a first memory for storing, consecutively, the coded data that can be entered in an order determined by the recording element affiliated with the control circuit -- a second memory for storing coded data to be recorded by said element -- a comparator connected to said two memories and controlled by an enabling circuit connected to a time base and to the recording element to cause the timely recording of the data recognized by comparison.