Abstract: A multiple control unit for selectively connecting a plurality of peripheral units to a central processor comprising a register for storing the interruptions coming from the peripherals; a disabling circuit for disabling the cell storing the interruption executed by the central processor in response to an end-of processing signal generated from the CPU.

Abstract: A modular minicomputer is provided which is assembled from a central processor unit module and a plurality of memory modules. Small calculators on the memory modules are so interlocked that when the computer is powered up, memory address boundaries are calculated automatically. As a result, the bank of memory modules appears to the central processing unit the same as a single large memory unit.

Abstract: One of a series of hardware/firmware primitives is disclosed for converting a general purpose digital computer into a database machine. The invention comprises a hardware/firmware implemented machine instruction called the find owner instruction, which fetches a set descriptor, which along with a base register BR, allows access to the owner pointer of a member record. The address of the owner record is then loaded into a register or registers.

Abstract: One of a series of hardware/firmware primitives is disclosed for converting a general purpose digital computer into a database machine. The invention comprises a hardware/firmware implemented machine instruction which sequentially checks each database record in a database area beginning at the page/line number address (database address) contained in a register, until the next active record is located. The database address of that active record is then loaded into a register.

Abstract: A programmable system controller stores in memory a sequence of program words directly simulating a planar ladder diagram characterizing the desired operation of a controlled system. The ladder diagram is a set of n rung-by-m column arrays of contacts interconnected with particular controlled devices of the system. The program words are read out of the memory in a sequence to directly represent the ladder diagram on a rung-by-rung basis for each column. The controller includes an interface unit coupled to a set of input switches for providing switch signals that are indicative of the operating status of the machine. A data processing unit is provided with an accumulator having a plurality of at least n storage units respectively corresponding to each rung of the ladder diagram.

Abstract: A biprogrammable computer is provided with an operator actuable selector switch. Each position of the selector switch of the computer assigns the keyboard, the console and the display to a selected one of the two programs in progress, so that the data entered by the keyboard is automatically transferred to the memory zone allocated to the program selected at the same time the display displays messages of the selected program. If the program not selected by the selector switch must alert the operator to some abnormalities, it activates a lamp and an associated buzzer. The operator after the end of the keyboard operation, actuates the selector switch and removes the cause of the abnormality. Registers are provided for storing the point of interruption of a program being processed, as well as information for determining if the data being entered by the keyboard relates to the program selected.

Abstract: Data transfer and control apparatus for coupling between a data source having a first character per second rate of delivery of coded pulse groups each representing a character and a recorder for recording data in blocks of a fixed number of characters at a second character per second rate comprising an incremented data storage register; an incremented tag signal storage register; means for applying coded pulse groups to said register from said source; means for providing tag signals, associated with respective applied coded pulse groups, to said tag signal register; means for incrementing said applied pulse groups and associated tag signals synchronously in their respective registers at a third character per second rate.

Abstract: A data-processing system for pattern-recognition and the like, having an instruction unit (IU) for storing, decoding and modifying instructions, and an execution unit (EU) for storing and performing operations on data. The IU has facilities for making a branch address effective for a plurality of subsequent instructions, and for masking and de-conditioning the prospective branch. The IU also indexes data-operand addresses according to a variable modulus. The EU performs Boolean and voting logic functions in a series of cascaded registers. The EU controls the acquisition of external data according to the type of instruction being executed, and maintains a record of the location of data strings in memory. Intermediate computational results are automatically placed in a hardware stack without any programming overhead. Bits from multiple operands are placed in a single operand byte by shift-load instructions.

Abstract: A firmware/hardware mechanism in a general purpose computer system automatically provides alternate addressing paths for addressing data in the same or another main memory module when a failure is detected in a portion of the main memory or main memory module. Two types of memory failures are detected and an alternate path provided for each type of failure. The first type is a failure in a memory which is not detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an exception processing mechanism to provide an alternate path to a good memory module. The second type of failure is detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an interrupt processing mechanism to provide an alternate path to a good memory module.

Abstract: Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. This first input is connected to circuitry which is enabled by a signal from a bit of a condition code register on the microprocessor chip which bit, is set, acts to mask or disenable the interrupt signal, so that the instruction execution operation of the microprocessor chip is not interrupted. A second input of a microprocessor chip is adapted to having a second interrupt signal applied thereto. The second input is connected to other input circuitry which is not enabled by the mask bit of a condition code register. Therefore, the second input acts as a non-maskable interrupt input.

Abstract: A control unit supplies information and includes a memory for storing information. A data bus connected to the control unit transfers the information. A controlled unit connected to the data bus receives information transferred from the control unit. The controlled unit comprises a plurality of n circuit stages, wherein n is a whole number, connected in tandem. The controlled unit includes first to n.sup.th circuit stages and an i.sup.th circuit stage intermediate the first and n.sup.th circuit stages and designated by the control unit. Information transferred from the control unit is stored in the first circuit stage and is transferred sequentially from the first to the i.sup.th circuit stages. Information stored in the first to (i-1).sup.th circuit stages is transferred to the memory of the control unit via the data bus for storage in the memory when the control unit requires alteration of information stored in the i.sup.th circuit stage.

Abstract: Intermixing of line heights in a buffered printer is accomplished by storing a different byte in a forms control buffer for each line of coded character data in a page to be printed. As the coded data of each line is advanced for printing by an arrangement which modulates a laser beam during scanning across a printable medium to effect the printing, the byte within the forms control buffer corresponding to the line about to be printed causes selection of the number of scans of the laser beam to be used in printing the line, thereby determining the height of each line independently of the other lines in the page. Blank lines in the page are formed by channel commands to the printer which instruct an address register associated with the forms control buffer to be incremented to cause skipping to a particular channel number identified by one of the bytes in the forms control buffer or to cause spacing by a specified number of lines.

Abstract: An industrial process controller provides an operator with a panel through which a program may be stored, reviewed, altered during review, and run without involving complex peripheral equipment.

Abstract: In a buffered printer in which lines of character code bytes representing characters to be printed are translated into lines of graphic code bytes by a translate table, assembled into a page format in a page buffer and applied to a character generator module to select sets of character image bits in storage locations within the module corresponding to the graphic code bytes, the selected sets of character image bits being applied to modulate a scanning laser beam to effect printing of the desired characters, each line of graphic code bytes provided by the translate table is entered into the page buffer in a selected location determined by a channel command associated with the previously entered line. Each "write and no space" command accompanying a line of graphic code bytes stored in the page buffer results in the immediately following line of graphic code bytes being stored in the same location. The two different lines are combined in accordance with a merge algorithm.

Abstract: A digital controller comprises digital operating and processing means including an offering signal input terminal, an answerback signal input terminal, a data output bus, an input and output device designating bus, and a control signal bus; a plurality of output registers; a flip-flop circuit for storing an offering signal; a decoder circuit responsive to signals from the input and output designating bus and from the control signal bus to produce a control signal corresponding to a code signal for the decoder circuit when the code signal is designated and to reset an output register designated by a particular bit of the data output bus in response to a signal generated by a signal impressed upon the answerback signal input terminal to reset the flip-flop circuit for storing the offering signal; said plurality of register circuits being connected to receive an output signal from the operating and processing means designated by a particular bit of the data output bus; an offering signal holding circuit to hold

Abstract: A system for the field recording of seismic data in which a large plurality of geophones are arrayed on the earth and divided into groups, and each group is connected to an array terminal. All of the array terminals are connected in series, by cables, with the last terminal connected to a recording unit. In each of the terminals there are means to process the geophone analog signals by amplifying at constant gain and digitizing to 1 bit to provide a plurality of 1 bit pulses, which are stored in parallel in a parallel to serial convertor.

Abstract: A data-processing system for pattern-recognition and the like, having an instruction unit (IU) for storing, decoding and modifying instructions, and an execution unit (EU) for storing and performing operations on data. The IU has facilities for making a branch address effective for a plurality of subsequent instructions, and for masking and de-conditioning the prospective branch. The IU also indexes data-operand addresses according to a variable modulus. The EU performs Boolean and voting logic functions in a series of cascaded registers. The EU controls the acquisition of external data according to the type of instruction being executed, and maintains a record of the location of data strings in memory. Intermediate computational results are automatically placed in a hardware stack without any programming overhead. Bits from multiple operands are placed in a single operand byte by shift-load instructions.

Abstract: A microprogram control system includes first and second control stores. The first is a pathfinder control store which is addressed initially by the operation code of a program instruction for read out of first and second addresses. The first address is used for accessing a standard microinstruction sequence during a first phase of operation. The second address is used for accessing an execution microinstruction sequence during a second phase of operation, both phases being required for executing the operation specified by the operation code of the program instruction. Means coupled to the second control store enable the control store to return to the standard microinstruction sequence following the completion of the second phase of operation when the instruction being executed requires the completion of additional operations before its execution can be terminated.

Abstract: A character generator for full page, raster scan printing is controlled to sequentially generate parts of different characters in a single scan. Further the character generation control independently stores for each row of text to be generated, the order position of a character or symbol being generated and the remaining number of raster scans required to complete generation of the symbol. Use of this control permits the sequential generation of parts of symbols even though the symbols have different relative widths and the full page raster scans are in a direction normal to the lines of text on the page. Use of the control also permits text assembly in a page memory to be generated in printed lines of text that extend either parallel or normal to the direction of light spot scanning by selecting predetermined alternative page memory access sequences.

Abstract: In a printer in which character code bytes representing characters to be printed are translated into graphic code bytes, assembled into lines and pages, and thereafter used to select character image bits which are applied to modulate a scanning laser beam and thereby effect printing of the characters, the pitch of each character is determined independently of other characters in each line being printed by pitch bits included in the sets of character image bits. As each scan line of modulation bits from a set of character image bits is selected for use in modulating the laser beam, the pitch bit included within the bits is examined to determine whether the width of the charactor is to be a maximum or some value less than the maximum. For the maximum width all of the modulation bits are applied to modulate the laser beam, while for a character cell width less than the maximum, only a selected number of the modulation bits are used to modulate the laser beam.