Abstract: Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. To avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. The memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. If the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.

Abstract: The present technology relates to a storage device. According to the present technology, a memory controller controlling a memory device including a plurality of memory blocks may include an operation controller and a lifetime information controller. The operation controller may control the memory device to receive a write request from a host and perform a write operation on a selected memory block among the plurality of memory blocks. The lifetime information controller may generate lifetime information including a lifetime level of the selected memory block based on an erase and write count of the selected memory block.

Abstract: A data storage device and method for detecting malware on a data storage device. The device includes a non-volatile storage medium configured to store at least one file system control block and user data block(s) to store user data. The file system control block comprises at least one reference data structure. The data storage device further comprises a buffer to temporarily store user data. The data storage device further comprises a controller to scan each write command in the user data to be transferred for protocol commands or malicious data. The controller also stops the data transfer of user data from the buffer to the non-volatile storage medium if at least one of protocol commands or malicious data is detected in at least one write command.

Abstract: A memory access command to be performed on a die of a memory device is received, wherein the memory access command comprises a base partition number and a base page address. The memory access command is converted into a plurality of commands based on a number of partitions associated with the die. A respective partition number derived from the base partition number is determined for each command of the plurality of commands. A respective page address associated with each command of the plurality of commands is determined using the base page address. The plurality of commands is executed using, for each command of the plurality of commands, the respective partition number and the respective page address.

Abstract: A method for updating stored information and an apparatus. A controller performs error correction code (ECC) decoding on stored data information based on the stored data information and stored ECC check information to generate an error-corrected codeword, where the error-corrected codeword includes error-corrected data information. The controller generates candidate to-be-written data information based on the error-corrected data information and a data update indication. The controller performs a mask operation on the candidate to-be-written data information based on the stored data information, and writes unmasked content in the candidate to-be-written data information into a memory.

Abstract: Methods, systems, and devices for temperature-based scrambling for error control in memory systems are described. Techniques are described for a memory system to scramble data using different scrambling code parameters when writing the data at different temperatures. Scrambling the data using scrambling code parameters that are based on the temperatures at the time or writing the data may reduce errors introduced into the data by operating the memory cells at extreme temperatures.

Abstract: A storage device set is provided. The storage device set includes a reconfigurable logic chip and a storage device. The logic chip includes a retimer configured to generate an output signal by adjusting an input signal received from an external device; and an operation circuit configured to perform an operation function. The storage device includes: a first port connected to the retimer; a second port connected to the operation circuit; and a controller configured to control data transmission and reception via the first port and the second port.

Abstract: A method for striping, the method may include performing, for each period of time out of multiple periods of time, the steps of: (i) determining striping rules; wherein the determining of the striping rules may include selecting one or more selected stripe size values out of multiple stripe size value candidates; wherein the selecting is based on values of storage system parameters that are obtained when applying the multiple stripe size value candidates; wherein the storage system parameters comprise storage space utilization and storage system throughput; and (ii) applying the striping rules by the storage system, during the period of time; wherein the applying comprises obtaining data chunks; converting the data chunks to stripes having at least one of the one or more selected stripe size values; and storing the stripes in the storage system.

Abstract: An accelerator is disclosed. The accelerator may include a memory that may store a dictionary table. An address generator may be configured to generate an address in the dictionary table based on an encoded value, which may have an encoded width. An output filter may be configured to filter a decoded value from the dictionary table based on the encoded value, the encoded width, and a decoded width of the decoded data. The accelerator may be configured to support at least two different encoded widths.

Abstract: A system for data migration is disclosed. The system may receive a migration request comprising a source file path and a target file location. The system may capture source file metadata based on the source file path and the migration request. The system may transfer a source file from a first data environment to an intermediate data environment via a first transfer process. The system may transfer the source file from the intermediate data environment to a second data environment via a second transfer process.

Abstract: Provided a data management system which includes a data acquisition unit that acquires measurement data obtained by measuring a fluid flowing in a flow path from each of a plurality of sensors, a data recording unit that records the acquired measurement data, and a data volume reduction unit that reduces a data volume to be recorded for a target sensor based on the measurement data acquired from another sensor installed in either an upstream or a downstream from itself in the flow path among the plurality of sensors.

Abstract: Various embodiments, methods, and systems for erasure coding with overlapped local reconstruction codes, are provided. An erasure coding scheme can be defined based on Overlapped Local Reconstruction Codes (OLRC) that achieve high storage efficiency by providing fault tolerance properties that optimize reconstruction for common cases of failures while maintaining the reconstruction costs for uncommon case of failures. In operation, a data chunk is divided into data fragments. The data fragments correspond to zones. A plurality of parity fragments is computed using the data fragments. A parity fragment is computed using a subset of the data fragments. The plurality of parity fragments are assigned to the zones comprising the data fragments, where the data fragments and the plurality of parity fragments define overlapped local construction codes having a plurality of local groups. An unavailable data fragment is recoverable from at least two local groups from the plurality of local groups.

Abstract: A memory system, a memory controller and an operating method are disclosed. A first area, a second area included in the first area, and a third area are set. An area to which target data is to be written is determined to the first area or the third area. When the target data is written to the first area, the target data is preferentially written to the second area. The number of data bits stored per memory cell in the first area is less than the number of data bits stored per memory cell in the third area. As a consequence, it is possible to secure storage capacity of the memory system to at least a set reference while securing data write performance of the memory system recognized by a host to at least a set reference.

Abstract: A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, a function of the plurality of functions receives input/output (I/O) operations from a host computing system. The processing device further selects a first function of the plurality of functions to service and assigns a first operation weight to a first I/O operation type of I/O operations received at the first function and a second operation weight to a second I/O operation type of I/O operations received at the first function. The processing device also selects, for execution, a first number of operations of the first I/O operation type of the I/O operations received at the first function according to the first operation weight and a second number of operations of the second I/O operation type of the I/O operations received at the first function according to the second operation weight.

Abstract: A memory system includes: a memory device including a plurality of memory dies including the plurality of planes; and a controller configured to store data in a plurality of stripes each including physical pages of different planes and a plurality of unit regions, the controller comprising: a processor configured to queue write commands in a write queue, and select, among the plurality of stripes, a stripe in which data chunks corresponding to the write commands are to be stored; and a striping engine configured to receive queued orders of the write commands, and output, by referring to a lookup table, addresses of unit regions, in which the data chunks are to be arranged, to the processor, wherein the processor in configured to control the memory device to store the data chunks in the unit regions corresponding to the outputted addresses of the selected stripe.

Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.

Abstract: A request node is provided comprising request circuitry to issue write requests to write data to storage circuitry. The write requests are issued to the storage circuitry via a coherency node. Status receiving circuitry receives a write status regarding write operations at the storage circuitry from the coherency node and throttle circuitry throttles a rate at which the write requests are issued to the storage circuitry in dependence on the write status. A coherency node is also provided, comprising access circuitry to receive a write request from a request node to write data to storage circuitry and to access the storage circuitry to write the data to the storage circuitry. Receive circuitry receives, from the storage circuitry, an incoming write status regarding write operations at the storage circuitry and transmit circuitry transmits an outgoing write status to the request node based on the incoming write status.

Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

Abstract: A memory device to perform a calibration of read voltages of a group of memory cells. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine an amount of accumulated storage charge loss in the group of memory cells. Subsequently, the memory device can perform a read voltage calibration based on the determined amount of accumulated storage charge loss and a look up table.