Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. A computing system includes one or more clients for processing applications. A memory controller transfers traffic between the memory controller and two channels, each connected to a memory device. A client sends a 64-byte memory request with an indication specifying that there are two 32-byte requests targeting non-contiguous data within a same page. The memory controller generates two addresses, and sends a single command and the two addresses to two channels to simultaneously access non-contiguous data in a same page.

Abstract: A storage system in one embodiment comprises a plurality of storage devices and a storage controller. The storage system is configured by the storage controller to receive a plurality of data records in a count-key-data format, to separate count and key portions of the data records from remaining portions of the data records, to store the count and key portions of the data records in at least one designated page of a set of pages of a logical storage volume of the storage system, and to store the remaining portions of the data records in one or more other pages of the set of pages of the logical storage volume of the storage system. The designated page of the set of pages of the logical storage volume may comprise a first page of the set of pages, and the one or more other pages of the set of pages may comprise respective ones of a sequence of consecutive pages following the first page.

Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.

Abstract: Aspects of the present disclosure provide a computer-implemented method that includes providing a layered index to variable length data, the layered index comprising a plurality of layers. Each layer of the plurality of layers has an index array, a block offset array, and a per-block size array. The index array identifies a next level index of a plurality of indices or data. The indices represent a delta value from a first index of a block. The block offset array identifies a starting location of the index array. The per-block array identifies a shared integer size of a block of indices. The method further includes performing a random access read of the variable length data using the layered index.

Abstract: Apparatus comprises source circuitry to provide data items; buffer circuitry having a set of buffer entries to hold one or more data items, provided by the source circuitry, for delivery to one or more destinations within a respective delivery latency, in which a buffer entry holding an initial data item becomes available to hold another data item in response to delivery of the initial data item to its respective destination; and control circuitry to control acceptance of data items from the source circuitry for holding by the buffer circuitry, the control circuitry being configured to control the buffer circuitry to accept a given data item when: (i) a buffer entry is available to hold the given data item and (ii) the delivery latency of data items including the given data item held by the buffer circuitry is such that at least a threshold number of buffer entries may be made available within no more than a threshold availability period.

Abstract: A system for data migration is disclosed. The system may receive a migration request comprising a source file path and a target file location. The system may capture source file metadata based on the source file path and the migration request. The system may transfer a source file from a first data environment to an intermediate data environment via a first transfer process. The system may transfer the source file from the intermediate data environment to a second data environment via a second transfer process.

Abstract: A method for managing a cache memory of a storage system, the method may include receiving, by a controller of the storage system, an access request related to a data unit; wherein the receiving occurs while (a) the cache memory stores a group of oldest cached data units, and (b) the data unit is stored in a memory module of the storage system the differs from the cache memory; determining, by the controller, a caching category of the data unit; and preventing from caching the data unit in the cache memory when a hit score of the caching category of the data unit is lower than a hit score of the group of oldest cached data units; and caching the data unit in the cache memory when the hit score of the caching category of the data unit is higher than the hit score of the group of oldest cached data units; wherein the hit score of the caching category of the data unit is indicative of a probability of a cache hit per data unit of the caching category.

Abstract: A storage system comprises a disk array enclosure comprising an enclosure controller, a cache comprising a metadata journal, a plurality of data storage devices and a plurality of metadata storage devices. The enclosure controller is configured to write a stripe metadata page to the metadata storage devices that corresponds to a stripe of data stored on the data storage devices and to determine that the write of the stripe metadata page failed for a first metadata storage device. The enclosure controller is configured to add an entry to the metadata journal based on the determination that the write failed. The entry comprises an indication of the first metadata storage device and the stripe of data. The enclosure controller is configured to set an indication in a data structure associated with the disk array enclosure that the stripe metadata page has not been written to the first metadata storage device.

Abstract: A memory device to perform a calibration of read voltages of a group of memory cells. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine an amount of accumulated storage charge loss in the group of memory cells. Subsequently, the memory device can perform a read voltage calibration based on the determined amount of accumulated storage charge loss and a look up table.

Abstract: A processing system includes a cache, a host memory, a CPU and a hardware accelerator. The CPU accesses the cache and the host memory and generates at least one instruction. The hardware accelerator operates in a non-temporal access mode or a temporal access mode according to the access behavior of the instruction. The hardware accelerator accesses the host memory through an accelerator interface when the hardware accelerator operates in the non-temporal access mode, and accesses the cache through the accelerator interface when the hardware accelerator operates in the temporal access mode.

Abstract: A plurality of pieces of write data are aggregated on a buffer to obtain a segment where the segment exceeds a smallest write size supported by storage. An address on the storage is determined for the segment. Location information and identifier(s) associated with the segment are recorded where the location information points to the storage, as opposed to the buffer, while the write data is being aggregated. When the write data has been aggregated into the segment, the segment is written to the storage wherein the location information remains unchanged in response to the writing to the storage.

Abstract: Techniques for processing write operations may include: receiving, at a first data storage system, a first write operation that writes first data to a first device, wherein the first device is configured for replication on a second device of a second data storage system; performing first processing that determines whether the first data written by the first write operation is a duplicate of an existing entry in a first hash table of the first data storage system; responsive to determining the first data written by the first write operation is a duplicate of an existing entry in the first hash table, performing second processing; responsive to determining the first data written by the first write operation is unique and is not a duplicate of an existing entry in the first hash table, performing third processing; and transmitting the final buffer to the second data storage system.

Abstract: A method for performing a write operation in a distributed storage system is disclosed. The method comprises receiving a first time-stamped write request from a proxy server. Further, the method comprises determining if the first time-stamped write request is within a time window of a reorder buffer and if the first time-stamped write request overlaps with a second time-stamped write request in the reorder buffer. Responsive to a determination that the first time-stamped write request is outside the time window or that the first time-stamped write request is within the time window but has an older time-stamp than the second time-stamped write request, the method comprises rejecting the first time-stamped write request. Otherwise, the method comprises inserting the first time-stamped write request in the reorder buffer in timestamp order and transmitting an accept to the proxy server.

Abstract: The present invention realizes a storage device that has a high data reduction effect without decreasing I/O performances. The storage device includes a processor, an accelerator, a memory, and a storage medium, the processor specifies data to be compressed that is data stored in the storage medium from data stored in the memory and transmits a compression instruction including information relating to the data to be compressed to the accelerator, and the accelerator reads the plurality of continuous items of data from the memory and compresses the plurality of items of data to be compressed obtained by excluding data that is not to be compressed from the plurality of items of data, based on the information relating to the data to be compressed received from the processor, to generate compressed data stored in the storage device.

Abstract: Apparatus and method for improved cache utilization and efficiency on a many-core processor. An apparatus comprising: a plurality of execution units to generate cache access requests responsive to executing instructions; a pending request queue to store pending cache access requests generated by the execution units; pending queue management circuitry to compare a current cache access request with entries in the pending request queue to determine whether the current cache access request can be merged with an entry in the pending request queue and, if so, to merge the current cache access request with the entry.

Abstract: Techniques for evaluating data sets for compression processing may include: receiving first information for a data set, the first information including I/O activity information for the data set, a service level objective for the data set, and a size of the data set; determining, in accordance with the first information, whether the data set meets criteria indicating a specified level of importance and a specified level of I/O activity; responsive to determining the data set meets the criteria, sending second information identifying one or more storage objects of the data set to a compression engine, wherein the one or more storage objects of the data set are identified as having the specified level of importance and at least the specified level of I/O activity; and performing processing, by the compression engine using the second information, to determine whether to compress first data stored in the data set.

Abstract: A system and method for cache coherency within multiprocessor environments is provided. Each node controller of a plurality of nodes within a multiprocessor system receives a cache coherency protocol request from local processor sockets and other node controller(s). A ternary content addressable memory (TCAM) accelerator in the node controller determines if the cache coherency protocol request comprises a snoop request and, if it is determined to be a snoop request, searching the TCAM based on an address within the cache coherency protocol request. In response to detecting only one match between an entry of the TCAM and the received snoop request, sending a response to the requesting local processor a response without having to access a coherency directory.

Abstract: A method, computer program product, and computing system for compartmentalizing a plurality of RAID extents, within a RAID system, into a plurality of rotation subgroups. A write load imbalance condition is sensed in a first rotation subgroup, chosen from the plurality of rotation subgroups, that is associated with a plurality of logical data portions. At least one of the plurality of logical data portions is moved from the first rotation subgroup to a second rotation subgroup, chosen from the plurality of rotation subgroups.

Abstract: A method, computer program product, and computing system for compartmentalizing a plurality of RAID extents, within a RAID system, into a plurality of rotation subgroups. An IO overload condition is sensed in at least one drive extent associated with a first rotation subgroup, chosen from the plurality of rotation subgroups. Instructions are provided concerning moving at least a portion of a load experienced by the first rotation subgroup to a second rotation subgroup, chosen from the plurality of rotation subgroups.

Abstract: A method, computer program product, and computing system for compartmentalizing a plurality of RAID extents, within a RAID system, into a plurality of rotation subgroups. A first logical data portion is written to a first rotation subgroup chosen from the plurality of rotation subgroups. A wear imbalance condition is sensed in a first rotation subgroup, chosen from the plurality of rotation subgroups, that is associated with a plurality of logical data portions.