Patents Examined by Jared Rutz
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Patent number: 9715434Abstract: Techniques for data migration of a storage system are described herein. According to one embodiment, for at least one of segments of a file to be migrated from a source storage tier to a target storage tier, a fingerprint of the segment is transmitted to the target storage tier. In response to a response received from the target storage tier indicating that the segment has not been stored in the target tier based on the fingerprint, a storage space of the target tier estimated for migrating the file is incremented. One or more segments of the file that have not been stored in the target tier are migrated if the one or more segments of the file fit in the target storage tier based on the estimated storage space of the target tier.Type: GrantFiled: September 30, 2011Date of Patent: July 25, 2017Assignee: EMC IP Holding Company LLCInventors: Teng Xu, Windsor W. Hsu, Lan Chin
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Patent number: 9703710Abstract: A computer system has a plurality of processors with non-blocking memory caches. A controller sets an upper limit of allowed snoop commands for the computer system. The controller adjusts, using real-time bandwidth data of the computing system, the limit of snoop commands to a new numerical value. The controller detects that the snoop limit is being adjusted between snoop rates more than a threshold number of times. The controller designates an overriding limit of snoop commands in response to detecting the snoop limit being adjusted more than the threshold number of times. The overriding limit of snoop commands is fixed for a period of time. The controller delays snoop commands which exceed the overriding limit of snoop commands during the period of time.Type: GrantFiled: September 30, 2015Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Dharmesh Parikh, Gopikrishnan Viswanadhan
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Patent number: 9703711Abstract: A computer system has a plurality of processors with non-blocking memory caches. A controller sets an upper limit of allowed snoop commands for the computer system. The controller adjusts, using real-time bandwidth data of the computing system, the limit of snoop commands to a new numerical value. The controller detects that the snoop limit is being adjusted between snoop rates more than a threshold number of times. The controller designates an overriding limit of snoop commands in response to detecting the snoop limit being adjusted more than the threshold number of times. The overriding limit of snoop commands is fixed for a period of time. The controller delays snoop commands which exceed the overriding limit of snoop commands during the period of time.Type: GrantFiled: August 19, 2015Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Dharmesh Parikh, Gopikrishnan Viswanadhan
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Patent number: 9697127Abstract: A semiconductor device may include a pattern detector configured to select any one of a plurality of stride patterns as a detect pattern by referring to an input address, and the pattern detector may be configured to generate a prefetch address. The semiconductor device may also include a prefetch controller configured to generate a prefetch request according to the prefetch address generated by the pattern detector. The semiconductor device may also include a first storage unit configured to store prefetch data provided from a memory device according to the prefetch request generated by the prefetch controller, and a second storage unit configured to store prefetch data removed from the first storage unit.Type: GrantFiled: June 10, 2014Date of Patent: July 4, 2017Assignee: SK hynix Inc.Inventors: Jung-Hyun Kwon, Min-Sung Kang
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Patent number: 9697226Abstract: A method of storing a file in a storage system that includes a plurality of memory-storage hosts includes: providing unique chunk identifiers for memory chunks included in the file; using a hash mapping to identify one or more storage locations for each chunk identifier, each storage location corresponding to a portion of a memory-storage host; and storing each memory chuck at the corresponding one or more storage locations identified by the hash mapping.Type: GrantFiled: August 14, 2013Date of Patent: July 4, 2017Assignee: Sanmina CorporationInventor: Chris Youngworth
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Patent number: 9690694Abstract: An apparatus, system, and method are disclosed for storage address translation. The method includes storing, in volatile memory, a plurality of logical-to-physical mapping entries for a non-volatile recording device. The method includes persisting a logical-to-physical mapping entry from the volatile memory to recording media of the non-volatile recording device. The logical-to-physical mapping entry may be selected for persisting based on a mapping policy indicated by a client. The method includes loading the logical-to-physical mapping entry from the recording media of the non-volatile recording device into the volatile memory in response to a storage request associated with the logical-to-physical mapping entry.Type: GrantFiled: September 27, 2012Date of Patent: June 27, 2017Assignee: SanDisk Technologies, LLCInventors: David Nellans, Jens Axboe, Nick Piggin
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Patent number: 9684471Abstract: Various embodiments for priority based depopulation of ranks in a computing storage environment are provided. In one embodiment, a method comprises prioritizing a plurality of ranks selected for depopulation. Highest priority and lowest priority ranks are marked and selected for depopulation. Lower priority ranks are placed in a queue in order of priority. An extent of one of the lower priority ranks is migrated to a rank not selected for depopulation. One of the lower priority ranks with newer data is selected for executing a read operation in response to a read operation to one of the lower priority ranks. At least one of the highest priority ranks is depopulated to at least one of a plurality of targeted ranks. The highest priority rank is left as unassigned to one of the plurality of targeted ranks until determining if the highest priority rank is to be assigned the targeted ranks.Type: GrantFiled: December 10, 2015Date of Patent: June 20, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Juan A. Coronado, Jennifer S. Shioya, Todd M. Tosseth
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Patent number: 9678872Abstract: A method and apparatus for memory paging is disclosed. A system includes a plurality of processor cores each configured to initiate requests to a memory by providing a physical address without a virtual address. A first cache subsystem is shared by each of a first subset of the plurality of processor cores. Responsive to receiving a memory access request from a processor core of the first subset, the first cache subsystem determines if a physical address of the request is in a first paged region of memory with respect to the first subset. If the physical address is in the paged region, the cache subsystem is configured to access a set of page attributes for a page corresponding to the physical address from a page attribute table responsive that is shared by each of the first subset of the plurality of processor cores.Type: GrantFiled: January 16, 2015Date of Patent: June 13, 2017Assignee: Oracle International CorporationInventor: John Fernando
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Patent number: 9678665Abstract: Techniques for improving memory page allocation are disclosed. In some embodiments, the techniques may be realized as a method for improving memory page allocation including generating, using a compression unit, compressed grains associated with compressed blocks, identifying a write page allocation unit to query, receiving, at the write page allocation unit, a query for a flash memory location to store the compressed grains, determining a flash memory location for the compressed grains, determining a parity location for the compressed grains, returning offsets indicating the flash memory location and the parity location, sending the compressed grains to the free grain location and a parity bit to the parity location as part of an atomic transaction, and recording a start location of compressed grains in a mapping.Type: GrantFiled: March 6, 2015Date of Patent: June 13, 2017Assignee: Western Digital Technologies, Inc.Inventors: Vijay Karamcheti, Ashwin Narasimha, Ashish Singhai
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Patent number: 9672159Abstract: A data processing system 2 incorporates a translation buffer unit 24, 26, 28 and a translation control unit 30. The translation buffer unit responds to receipt of a memory access transaction for which translation data is unavailable in that translation buffer unit by issuing a request to the translation control unit to provide translation data for the memory access transaction. The translation control unit is responsive to disabling or enabling of address translation for a given type of memory access transaction to an issue invalidate command to all translation buffer units which may be holding translation data for that given type of memory access transaction.Type: GrantFiled: July 2, 2015Date of Patent: June 6, 2017Assignee: ARM LimitedInventors: Andrew Brookfield Swaine, Viswanath Chakrala
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Patent number: 9665291Abstract: A method and an apparatus for tiered storage processing of data, and a storage device. The method includes: splitting the migration unit into multiple migration subunits when a migration unit of low-tier disks is migrated to high-tier disks, and detecting a data access frequency of each migration subunit respectively; migrating the migration subunit to the low-tier disk when detecting that the data access frequency of the migration subunit is lower than a set threshold; and combining the multiple migration subunits into the migration unit when detecting that the multiple migration subunits are all migrated to the lower-tier disk. The present invention improves usage of storage media, and controls metadata storage resource consumption effectively.Type: GrantFiled: February 26, 2014Date of Patent: May 30, 2017Assignee: Huawei Technologies Co., Ltd.Inventors: Yu Lin, Shangdong Liang
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Patent number: 9665296Abstract: The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. These embodiments include techniques to use both volatile memory and non-volatile swap memory to pre-load a plurality of applications, to control the bandwidth of swap operations, to encrypt data stored in the swap area, and to perform a fast clean-up of the swap area.Type: GrantFiled: May 7, 2014Date of Patent: May 30, 2017Assignee: SanDisk Technologies LLCInventors: Robert S. Wu, Jian Chen, Ashish Karkare, Alon Marcu, Vsevolod Mountaniol
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Patent number: 9652335Abstract: A system and method for communicating, browsing, verifying and routing data in storage operation systems using network attached storage devices is provided. In some embodiments, the system may include a management module and a media management component connected to the management server, which interoperate with network attached storage devices to provide the communicating, browsing, verifying and routing functions.Type: GrantFiled: June 28, 2016Date of Patent: May 16, 2017Assignee: Commvault Systems, Inc.Inventors: Duncan Littlefield, Ho-chi Chen, Rajiv Kottomtharayil
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Patent number: 9645746Abstract: Systems and methods are provided for supporting use of non-volatile memory (NVM) on a double data rate (DDR) memory channel for an information handling system so that non-volatile memory devices (e.g., such as Phase Change Memory “PCM” devices) may be employed for main memory usage. In one possible implementation, information handling system memory reads may be managed directly in hardware as memory semantics via use code, while memory writes may be separately handled, e.g., via an operating system (OS)/driver. In another possible implementation, both DRAM-based and NVM-based memory systems may be populated for an information handling system.Type: GrantFiled: January 18, 2016Date of Patent: May 9, 2017Assignee: Dell Products L.P.Inventors: Stuart Allen Berke, Shawn J. Dube
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Patent number: 9639423Abstract: A system including first and second memory and a control module. The first memory stores a first lookup table with first metadata that includes a first mapping between logical and physical addresses and is lost due to an unexpected power down event. The second memory stores a second lookup table with second metadata and an event log. The second metadata includes a second mapping between the logical and physical addresses. The event log includes entries indicating updated associations between respective ones of the logical addresses and one of the physical addresses as included in the first metadata prior to the power down event. The control module: prior to the power down event, performs segmented flushes each including updating a segment of the second metadata with a corresponding segment of the first metadata; and walks the event log to recover a full flush cycle of segments of the first metadata.Type: GrantFiled: November 11, 2014Date of Patent: May 2, 2017Assignee: MARVELL WORLD TRADE LTD.Inventors: Jason Adler, Perry Neos, Luan Ton-That, Gwoyuh Hwu
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Patent number: 9639399Abstract: A method is provided for memory releasing. The method includes obtaining a first memory space value of a terminal system, where the first memory space represents a size of current idle memory space on the terminal system. The method also includes requesting a memory space whose size equals to a second memory space value from the terminal system, where the second memory space value is greater than the first memory space value. Further, the method includes releasing occupied memory after the terminal system receives a memory space request and detects that the second memory space value is greater than the first memory space value. The method includes confirming allocation of the memory space whose size equals to the second memory space value. The method includes releasing the memory space whose size equals to the second memory space value as the idle memory space after receiving allocation confirmation of the memory space of the terminal system.Type: GrantFiled: April 7, 2014Date of Patent: May 2, 2017Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Zebin Chen, Haifeng Ding
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Patent number: 9639465Abstract: A method and apparatus for controlling a frequency of CMI are disclosed. The method may include classifying request types into one or more request groups, wherein each of the request types is a type of CMI request. A number of clock cycles that is sufficient to process a request in each request group may be assigned, and requests that are made to CMI may be monitored with one or more performance counters. A number of requests that occur during a length of time in each request group may be determined, and a frequency of the CMI may be periodically adjusted based upon the number of requests occurring per second in each request group and the assigned number of clock cycles per request for each request group.Type: GrantFiled: February 24, 2015Date of Patent: May 2, 2017Assignee: Qualcomm Innovation Center, Inc.Inventor: Saravana Krishnan Kannan
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Patent number: 9632722Abstract: A method begins by a processing module determining to move a range of encoded data slices from a first storage unit to a second storage unit of a plurality of storage units, where data objects are dispersed storage error encoded to produce pluralities of sets of encoded data slices, and where the pluralities of sets of encoded data slices are stored in the plurality of storage units. The method continues with the processing module transferring the range of encoded data slices from the first storage unit to the second storage unit. In response to the transferring the range of encoded data slices from the first storage unit to the second storage unit, the method continues with the processing module transferring a corresponding range of second encoded data slices from a third storage unit to a fourth storage unit.Type: GrantFiled: August 13, 2014Date of Patent: April 25, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Manish Motwani
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Patent number: 9619175Abstract: A method of operating an eMMC system includes receiving a first command defining a first operation from the host, and storing the first command in a first command register among N command registers, and receiving a second command defining a second operation from the host, and storing the second command in a second command register among the N command registers, wherein the second command is received while the first operation is being performed.Type: GrantFiled: September 13, 2013Date of Patent: April 11, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Woon Jae Chung, Song Ho Yoon
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Patent number: 9619400Abstract: A computer-implemented method for managing memory operations includes reading a first memory page from a storage device responsive to a request for the first memory page. The first memory page is stored to a system memory. Based on a pre-established set of association rules, one or more associated memory pages are identified that are related to the first memory page. The associated memory pages are read from the storage device and compressed to generate corresponding compressed associated memory pages. The compressed associated memory pages are also stored to the system memory to enable memory access to the associated memory pages during processing of the first memory page. The compressed associated memory pages are individually decompressed in response to the particular page being required for use during processing.Type: GrantFiled: February 28, 2013Date of Patent: April 11, 2017Assignee: International Business Machines CorporationInventors: Saravanan Devendran, Kiran Grover