Patents Examined by Jared Rutz
  • Patent number: 9483401
    Abstract: Embodiments of the present invention disclose a data processing method and apparatus. The method includes: first receiving an operation command, then searching, according to a memory address, a Cache memory in a Cache controller for data to be operated, and storing the operation command in a missed command buffer area in the Cache controller when the data to be operated is not found through searching in the Cache memory; then, storing data sent by an external memory in a data buffer area of the Cache controller after sending a read command to the external memory, and finally processing, according to a missed command, the data acquired from the external memory and the data carried in the missed command. The present invention applies to the field of computer systems.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: November 1, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yongbo Cheng, Tao Li, Chenghong He
  • Patent number: 9483415
    Abstract: An apparatus for managing a memory including a working region and a compression region is provided. The working region stores uncompressed data. The apparatus includes a management module and a compression/decompression module. According to a recent used index and a compression ratio of a set of target data stored in the working region, the management module determines whether to transfer the target data to the compression region. When the management module determines to transfer the target data to the compression region, the compression/decompression module compresses the target data and transfers the compressed target data to the compression region.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 1, 2016
    Assignee: MStar Semiconductor, Inc.
    Inventors: Yi-Shin Tung, He-Yuan Lin, Jia-Wei Lin, Hung-Wei Yang
  • Patent number: 9483358
    Abstract: A method, article of manufacture, and apparatus for protecting data. In some embodiments, this includes identifying a parent virtual container, identifying a linked child virtual container, creating a fast copy of the parent virtual container and the linked child virtual container, and consolidating the copy of the parent virtual container and the copy of the linked child virtual container based on the format of the parent virtual container.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 1, 2016
    Assignee: EMC IP Holding Company LLC
    Inventors: Shankar Balasubramanian, Vladimir Mandic, Sriprasad Bhat Kasargod, Anand Raj
  • Patent number: 9477558
    Abstract: Logging changes to a physical memory region during a logging time interval includes: detecting a write operation to the physical memory region, wherein the write operation modifies an indirect representation that corresponds to a physical data line in the physical memory region; and recording log information associated with the write operation.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventor: David R. Cheriton
  • Patent number: 9477422
    Abstract: In a storage system including plural source storage devices, a target storage device selects which source storage device to accept a copy request from the target storage device so as to minimize the load on the entire system. The system calculates first and second load values for job loads being processed. System load values for the system are derived from job load value of a specific data, and respective load values for first and second source storage devices. The system compares the system load values to select a storage device to provide the data copy so as to minimize the load on the entire system.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: October 25, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Norie Iwasaki, Katsuyoshi Katori, Takeshi Nohta, Kohei Taguchi, Eiji Tosaka
  • Patent number: 9478312
    Abstract: Described herein are techniques, systems, and circuits for addressing image data according to blocks. For example, in some cases, the address space may be divided into high order address bits and low order address bits. In these cases, an address circuit may twist an address space by shifting the high order bits and low order bits of an address in a rightward direction, shifting the low order bits of the address in a leftward direction, and shifting the high order bits and the low order bits of the address in the leftward direction. The circuit may modify the address value and untwist the address space. For example, the untwisting may include shifting the high order bits and the low order bits of an address in the rightward direction, shifting the low order bits of the address in the rightward direction, and shifting the high order bits and the low order bits of the address in the leftward direction.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 25, 2016
    Assignee: Amazon Technologies, Inc.
    Inventor: Carl Ryan Kelso
  • Patent number: 9471346
    Abstract: Embodiments of the present invention provide hints for page stealing by prioritizing pages based on the number of residences. Receiving a plurality of pages to be hinted to a hypervisor for page stealing. Determining at least two page types of the plurality of pages. Determining whether any of the at least two page types has a total number of residences less than a total number of potential residences in the virtual environment for all page types and have a total number of residences less than a threshold. Responsive to determining a first page type of the at least two page types has a total number of residences less than a total number of potential residences for all page types and has a total number of residences less than a threshold, notifying the hypervisor of at least one page from the plurality of pages that is the determined first page type.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Chetan L. Gaonkar, Chidambar Y. Kulkarni, Lakshmi Priya, Vamshi K. Thatikonda
  • Patent number: 9471495
    Abstract: Embodiments of the present invention provide a method and an apparatus for constructing a memory access model, and relate to the field of computers. The method includes: obtaining a page table corresponding to a process referencing a memory block, and clearing a Present bit included in each page table entry stored in the page table; and constructing a memory access model of the memory block according to the number of access times of each page in the memory block and time obtained through timing, where the memory access model at least includes the number of access times and an access frequency of each page in the memory block. The apparatus includes: a first obtaining module, a first monitoring module, a first increasing module, and a second obtaining module. The present invention can reduce the memory consumption and an impact on the system performance, and avoid a system breakdown.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: October 18, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yiyang Liu, Wei Wang, Xishi Qiu
  • Patent number: 9459801
    Abstract: According to one embodiment, a tiered storage system includes a high-speed storage device, a low-speed storage device, and a storage controller. The storage controller interchanges a location destination of data of a first logical chunk to which a third storage area of the low-speed storage device is allocated and a location destination of data of a second logical chunk to which a first storage area of the high-speed storage device is allocated and whose access frequency statistical value is smaller than that of the first logical chunk. The storage controller reallocates a second storage area of the high-speed storage device to a set of logical chunks to which the third storage area is allocated.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 4, 2016
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Solutions Corporation
    Inventor: Atsushi Asayama
  • Patent number: 9459811
    Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system includes a first disk and a second disk. The data processing method includes: receiving a reading command, wherein the reading, command includes a data starting address; determining to assign the reading command to the first disk or the second disk according to the data starting address of the reading command and a stripe size; and reading corresponding data according to the reading command from the first disk or the second disk which receives the reading command.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: October 4, 2016
    Assignee: ASMEDIA TECHNOLOGY INC.
    Inventors: Ming-Hui Chiu, Chia-Hsin Chen, Yung-Chi Hwang, Ching-Fa Hsiao
  • Patent number: 9454480
    Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: September 27, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Eitan Joshua, Erez Amit, Shaul Chapman, Sujat Jamil, Frank O'Bleness
  • Patent number: 9454489
    Abstract: When a request is made to retrieve a guest physical page from memory and a page fault occurs, a guest virtual page address that corresponds to the guest physical page is identified along with addresses for guest virtual pages that are near the guest virtual page in the virtual address space. Each identified guest virtual page address is translated into a corresponding guest physical page address and the corresponding guest physical pages are loaded into memory.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: September 27, 2016
    Assignee: VMware, Inc.
    Inventors: Kiran Tati, Gabriel Tarasuk-Levin, Ka Wing Ho, Jesse Pool
  • Patent number: 9454475
    Abstract: A control device includes a control unit that performs a writing control of supplied host data, according to a data writing request from a host apparatus, with respect to a non-volatile memory where multi-value storage with 2 bits or more is performed in one memory cell, having a lower level page and an upper level page for at least the multi-value storage as a physical page in which a physical address is set, and where data writing is performed using each physical page in an order of physical addresses, and that causes the data writing to be performed until the physical page immediately before the lower level page, such that the data writing according to a next data writing request is started from the lower level page.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: September 27, 2016
    Assignee: Sony Corporation
    Inventor: Yuya Ishikawa
  • Patent number: 9454310
    Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 27, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Victor Y. Tsai, Danilo Caraccio, Daniele Balluchi, Neal A. Galbo, Robert Warren
  • Patent number: 9454306
    Abstract: Workload on an aggregation of storage devices can be quantified in terms of demand on the aggregation of storage devices and demand on logical storage containers configured on the aggregation of storage devices. The demand on the aggregation of storage devices and the demand on logical storage containers thereon are calculated in a manner that captures demand on both storage capacity and performance capability. Capturing demand on both storage capacity and performance capability facilitates intelligent management that accounts for the relationship between storage capacity and performance capability. This allows the owner/operator of the storage equipment to use storage capacity at a desired (or requested) performance.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: September 27, 2016
    Assignee: NETAPP, INC.
    Inventors: Lewis R. Newby, Jr., Kelly Hemphill
  • Patent number: 9448742
    Abstract: Communication between a host and a data storage device (DSD) including a first media for storing data and a second media for storing data. In one embodiment, a first controller of the DSD is configured to control operation of the first media and a second controller of the DSD is configured to control operation of the second media. The first controller receives a key data block of a monitoring system from the host with the key data block including a task file. The key data block is evaluated to determine if the key data block is directed to the second media, and if it is determined that the key data block is directed to the second media, the task file of the key data block is sent from the first controller to the second controller.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: September 20, 2016
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jonathan K. Cheng, Si Ho
  • Patent number: 9448729
    Abstract: A method and system for implementing paging optimization to avoid populate on page fault during an Input Output (IO) read. A size of the IO read is evaluated. If the IO does not entirely cover a page, then the page is paged in. If the IO entirely covers one or more pages, those pages are not paged in. Page attributes may be different during the IO read. Pages that are paged in are marked readable and writable but pages that are waiting for the IO to populate them are only marked writeable. Once the IO read has completed, the pages are marked readable and writable and all outstanding faults due to reads during this window are completed.
    Type: Grant
    Filed: April 25, 2015
    Date of Patent: September 20, 2016
    Assignee: International Business Machines Corporation
    Inventor: Adrian C. Gerhard
  • Patent number: 9442845
    Abstract: The present invention relates to the field of communication technologies and discloses a method and an apparatus for encoding a data address, so that attacks can be effectively prevented and resources and costs required to handle a bank conflict are reduced. In solutions provided by embodiments of the present invention, an exclusive-OR operation is performed on one or more bits of a received uncoded address by using multiple preset transform polynomials; and an encoded address is obtained according to a result of the exclusive-OR operation. The solutions provided by the embodiments of the present invention are applicable to designs that require a large-capacity DRAM, high performance and high reliability, and have an anti-attack demand.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 13, 2016
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chunlei Fan, Wenhua Du, Zixue Bi
  • Patent number: 9436405
    Abstract: Systems and methods are described for logical partitioning of library resources (e.g., storage media resources and/or media drive resources in storage libraries) across a complex of multiple, physically distinct, but logically interconnected data storage libraries. For example, a user selects complex-wide resources to add to one or more library partitions via a graphical user interface displayed on a local console of one of the storage library systems. The partitions can be validated and converted into a partition definition. In some implementations, the partition definition is redundantly stored as a predefined short format in local storage of some or all the storage library systems in the complex. This can minimize the resources used to store the partition definition, provide redundancy for added configuration options and/or in case of certain failures, speed up processing of resource queries, and/or provide other features.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: September 6, 2016
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Hyoungjin Kim, Alexander Edward Amador, Stephanie Lynn Russell
  • Patent number: 9436292
    Abstract: A cost function is determined for assigning first deduplicating storage units of a first storage system for replication onto second deduplicating storage units of a second storage system. One or more of the first storage units in the first storage system are assigned to one or more of the second storage units in the second storage system based on a minimized cost resulting from the cost function.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 6, 2016
    Assignee: EMC Corporation
    Inventors: Frederick Douglis, R. Hugo Patterson, Philip N. Shilane