Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.

Abstract: An apparatus having a processor and a circuit is disclosed. The processor is generally configured to initiate an operation to recycle a plurality of source blocks in a memory that is nonvolatile. The circuit is generally configured to (i) search through a first of a plurality of levels in a map that defines a plurality of translations between a plurality of logical addresses used at an interface to a computer and a plurality of physical addresses used in the memory and (ii) notify the processor in response to a detection in the first level of one or more of the source blocks to be recycled that contain valid data.

Abstract: A system and method for determining an optimal cache size of a computing system is provided. In some embodiments, the method comprises selecting a portion of an address space of a memory structure of the computing system. A workload of data transactions is monitored to identify a transaction of the workload directed to the portion of the address space. An effect of the transaction on a cache of the computing system is determined, and, based on the determined effect of the transaction, an optimal cache size satisfying a performance target is determined. In one such embodiment the determining of the effect of the transaction on a cache of the computing system includes determining whether the effect would include a cache hit for a first cache size and determining whether the effect would include a cache hit for a second cache size different from the first cache size.

Abstract: A method, computer program product, and computing system for receiving, on an active storage processor from a passive storage processor, a join request indicator. The join request indicator indicates that the passive storage processor wants to transition to an active status. The active storage processor and the passive storage processor are both coupled to a data array. A status change indicator is provided from the active storage processor to the passive storage processor, wherein the status change indicator indicates that the passive-to-active transition of the passive storage processor has been initiated. A first data array status indicator is received on the active storage processor from the passive storage processor, wherein the first data array status indicator indicates the status of the data array as seen by the passive storage processor.

Abstract: A system and method for communicating, browsing, verifying and routing data in storage operation systems using network attached storage devices is provided. In some embodiments, the system may include a management module and a media management component connected to the management server, which interoperate with network attached storage devices to provide the communicating, browsing, verifying and routing functions.

Abstract: Systems capable of transformation of logical data objects for storage and methods of operating thereof are provided. One method includes identifying among a plurality of requests addressed to the storage device two or more “write” requests addressed to the same logical data object, deriving data chunks corresponding to identified “write” requests and transforming the derived data chunks, grouping the transformed data chunks in accordance with the order the requests have been received and in accordance with a predefined criteria, generating a grouped “write” request to the storage device, and providing mapping in a manner facilitating one-to-one relationship between the data in the obtained data chunks and the data to be read from the transformed logical object. The method further includes obtaining an acknowledging response from the storage device, multiplying the obtained acknowledging response, and sending respective acknowledgements to each source that initiated each respective “write” request.

Abstract: Systems capable of transformation of logical data objects for storage and methods of operating thereof are provided. One method includes identifying among a plurality of requests addressed to the storage device two or more “write” requests addressed to the same logical data object in a distributed network, deriving data chunks corresponding to identified “write” requests and transforming the derived data chunks, grouping the transformed data chunks in accordance with a predefined criteria, generating a grouped “write” request to the storage device, and providing mapping in a manner facilitating one-to-one relationship between the data in the obtained data chunks and the data to be read from the transformed logical object. The method further includes obtaining an acknowledging response from the storage device, multiplying the obtained acknowledging response, and sending respective acknowledgements to each source that initiated each respective “write” request.

Abstract: The present disclosure provides techniques for cache management. A data block may be received from an IO interface. After receiving the data block, the occupancy level of a cache memory may be determined. The data block may be directed to a main memory if the occupancy level exceeds a threshold. The data block may be directed to a cache memory if the occupancy level is below a threshold.

Abstract: Various embodiments for storing a logical object are provided. In one such embodiment, by way of example only, incoming data is divided corresponding to a logical data object into a plurality of independent streams, associating each data chunk of a plurality of obtained data chunks with a corresponding stream among the plurality of independent streams. At least one of the obtained data chunks and derivatives thereof is sequentially accommodated in accordance with an order the obtained chunks are received, while keeping the association with the corresponding streams. A global index is generated as a single meta-data stream accommodated in the logical data object and comprising information common to the plurality of independent streams and related to mapping between data in the logical data object and the obtained data chunks.

Abstract: A computer determines an intrinsic read speed and an intrinsic write speed associated with a first disk and a second disk. The computer receives a request to read a portion of data, wherein the portion of data is stored redundantly on both the first and second disk. The computer identifies a first latency associated with reading the portion of data from the first disk, where the first latency is based on at least the intrinsic read speed and the intrinsic write speed associated with the first disk. The computer identifies a second latency associated with reading the portion of data form the second disk, wherein the second latency is based on at least the intrinsic read speed and the intrinsic write speed associated with the second disk. The computer determines that the first latency exceeds the second latency. The computer selects the second disk to read the portion of data.

Abstract: A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.

Abstract: A host for controlling a non-volatile memory card, a system including the same, and methods of operating the host and the system are provided. The method of operating the host connected with the non-volatile memory card through a clock bus, a command bus, and one or more data buses includes transmitting a first command to the non-volatile memory card through the command bus, transmitting first data corresponding to the first command to the non-volatile memory card through the one or more data buses or receiving the first data from the non-volatile memory card through the data buses, and transmitting a second command to the non-volatile memory card at least once through the command bus during or before transfer of the first data.

Abstract: Circuits and methods for performing search operations in a content addressable memory (CAM) array are provided. A system for searching a CAM includes a circuit that selectively activates a main-search of a two stage CAM search while a pre-search of the two stage CAM search is still active.

Abstract: In one aspect, a method includes checking periodically, using a processor, for a value associated with data in a data block in a higher tier journal stored on a first storage array having deduplication-based functionality and copying the data in the data block from the higher tier journal to a lower tier journal in a second storage array if the data in the data block exists only in an UNDO stream in the higher tier journal. The first storage array and the second storage array are used in a continuous data protection system to replicate a volume. The method also includes replacing the data in the data block in the journal with a zero block if the data in the data block exists only in the UNDO stream.

Abstract: Embodiments of the invention relate to a para-virtual I/O system. A consistent para-virtual I.O system architecture is provided with a new virtual disk interface and a semantic journaling mechanism. The virtual disk interface is extended with two primitives for flushing and ordering I/O, both of the primitives being exported to para-virtual I/O drivers in a guest operating system. The ordering primitive guarantees ordering of preceeding writes, and the flushing primitive enforces order and durability. The guest drivers selectively uses both of these primitives based on semantics of the data being persisted from the para-virtual cache hierarchy to physical disk. The order of committed writes is enforced in order to enable a consistent start recovered after a crash.

Abstract: A system comprises a host device and a cache controller. The host device includes a command buffer and a host application that posts a cache command that includes a cache key and a key aging alias in the command buffer. The cache controller includes logic circuitry configured to load the cache command from the command buffer of the first host device into the buffer memory, identify a match, if any, for the cache key in the command queue, perform the cache command, and return cache completion status information to the first host application, wherein the cache completion status information includes a value of the key aging alias in cache metadata when a match for the cache key is found and includes a value of the key aging alias provided by the first host application when a match for the cache key is not found.

Abstract: A semiconductor device includes a pipeline latch unit including a plurality of write pipelines, and suitable for latching data, and a control unit suitable for controlling at least one write pipeline of the write pipelines based on an idle signal.

Abstract: Techniques for reclaiming storage space are disclosed herein. According to one embodiment, a storage space reclamation method includes a storage host creating at least one temporary logical container of data in a storage volume managed by a file system of a host so that a predetermined portion of storage capacity of the storage volume is occupied. Access to the storage volume is provided by a network storage controller to the storage host. The storage host translates a host address range for the file system of each temporary logical container of data into a storage controller address range for the network storage controller. The storage host requests the network storage controller to deallocate blocks the locations of which are indicated by the storage controller address range, and then deletes the at least one temporary logical container of data.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for memory object reference count management with improved scalability based on transactional reference count elision. The device may include a hardware transactional memory processor configured to maintain a read-set associated with a transaction and to abort the transaction in response to a modification of contents of the read-set by an entity external to the transaction; and a code module configured to: enter the transaction; locate the memory object; read the reference count associated with the memory object, such that the reference count is added to the read-set associated with the transaction; access the memory object; and commit the transaction.

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.