Abstract: Implementation manners of the present invention provide a data storage method and apparatus. A fixed-length key and a value thereof are stored into a first data block, where the storing a fixed-length key includes: uniformly storing a common prefix of each fixed-length key, and separately storing a remainder part of each fixed-length key after the common prefix is removed; and a variable-length key and a length thereof are stored into a second data block, where the storing a variable-length key includes: storing a variable-length key of a base-key type in a full storage manner, and performing prefix compression on a variable-length key of a prefix-compressed key type.

Abstract: Disclosed herein are a semiconductor chip for adaptively processing a plurality of commands to request memory access, and a method of controlling memory. The semiconductor chip includes a storage unit ad a control unit. The storage unit stores a memory access request to be currently processed and a plurality of memory access requests received before the memory access request to be currently processed in received order. The control unit processes the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed, which have been stored in the storage unit, in received order, except that memory access requests attempting to access the same bank and the same row are successively processed.

Abstract: Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and reading from a register file may be energy and/or time intensive An operand cache may be used to store a subset of operands, and may use less power and have quicker access times than the register file. Selectors (e.g., multiplexers) may be used to read operands from the operand cache. Power savings may be achieved in some embodiments by activating only a subset of the selectors, which may be done by activators (e.g. flip-flops). Operands may also be concurrently provided to two or more locations via forwarding, which may be accomplished via a source selection unit in some embodiments. Operand forwarding may also reduce power and/or speed execution in one or more embodiments.

Abstract: In accordance with the present disclosure, a system and method are herein disclosed for managing memory defects in an information handling system. In an information handling system, a first quantity of memory, such as RAM, may contain defective memory elements. A second quantity of memory is physically coupled to the first quantity of memory and is used to store a memory defect map containing information regarding the location of defective memory elements in the first quantity of memory. The memory defect map may then be referenced by the BIOS or the operating system to preclude use of regions of memory containing defective memory elements.

Abstract: A data processing system includes a cache memory 58 and cache control circuitry 56 for applying a cache replacement policy based upon a retention priority value PV stored with each cache line 66 within the cache memory 58. The initial retention priority value set upon inserting a cache line 66 into the cache memory 58 is dependent upon either or both of which of a plurality of sources issued the access memory request that resulted in the insertion or the privilege level of the memory access request resulting in the insertion. The initial retention priority level of cache lines resulting from instruction fetches may be set differently from cache lines resulting from data accesses.

Abstract: A cache memory comprises a cache controller and a nonvolatile semiconductor memory as a storage medium. The nonvolatile semiconductor memory comprises multiple blocks, which are data erase units, and each block comprises multiple pages, which are data write and read units. The cache controller receives data and attribute information of the data, and, based on the received attribute information and attribute information of the data stored in the multiple blocks, selects a storage-destination block for storing the received data, and writes the received data to a page inside the selected storage-destination block.

Abstract: A memory device having a primary memory element, in which the memory device includes an evaluation device to ascertain whether the primary memory element experiences a state change and to activate a secondary memory element so that if (a) the primary memory element experiences a state change, the secondary memory element does not carry out a state change, and if (b) the primary memory element does not experience a state change, the secondary memory element carries out a state change.

Abstract: In one embodiment, a computing system includes a cache having one or more memories and a cache manager. The cache manager is able to receive a request to write data to a first portion of the cache, write the data to the first portion of the cache, update a first map corresponding to the first portion of the cache, receive a request to read data from the first portion of the cache, read from a storage communicatively linked to the computing system data according to the first map, and update a second map corresponding to the first portion of the cache. The cache manager may also be able to write data to the storage according to the first map.

Abstract: Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.

Abstract: Systems and methods for allocating memory usage based on voltage regulator efficiency are disclosed. According to an aspect, a method may include receiving a first efficiency value of a first voltage regulator associated with a first memory device among multiple memory devices. The method may also include receiving a second efficiency value of a second voltage regulator associated with a second memory device of the memory devices. The method may also include receiving a request to write data to one of the first memory devices and the second memory device. The method may also include determining whether to write the data to the first memory device or the second memory device based on the first and second efficiency values. Further, the method may include writing the data to the first memory device or the second memory device based on the determination.

Abstract: Methods for data storage, including configuring in a data storage system a volume storage pool as data storage resources available for allocation of volumes in the data storage system are disclosed. One method includes defining a threshold value for the volume storage pool. When the allocation of the volumes causes the threshold value to be crossed, the method includes performing an action for managing the volume storage pool.

Abstract: A network memory system is disclosed. The network memory system comprises a first appliance configured to encrypt first data, and store the encrypted first data in a first memory device. The first appliance also determines whether the first data is available in a second appliance and transmits a store instruction comprising the first data based on the determination that the first data does not exist in the second appliance. The second appliance is configured to receive the store instruction from the first appliance comprising the first data, encrypt the first data, and store the encrypted first data in a second memory device. The second appliance is further configured to receive a retrieve instruction comprising a location indicator indicating where the encrypted first data is stored, process the retrieve instruction to obtain encrypted response data, and decrypt the encrypted response data.

Abstract: Systems, methods and/or devices are used to enable storage drive life estimation. In one aspect, the method includes (1) determining two or more age criteria of a storage drive, and (2) determining a drive age of the storage drive in accordance with the two or more age criteria of the storage drive.

Abstract: A method includes, in a nonvolatile memory device that includes a plurality of dies, detecting that a first temperature associated with a first die is equal to or exceeds a temperature threshold. A metablock is defined to include a first plurality of storage blocks that includes a first storage block of the first die. Each storage block of the metablock resides in a distinct die of the plurality of dies. The method also includes, in response to detecting that the first temperature is equal to or exceeds the temperature threshold, redefining the metablock to exclude from the redefined metablock any storage block associated with the first die.

Abstract: A plurality of storage apparatuses including a first and second storage apparatus, wherein said first storage apparatus is configured to have a first virtual volume composed of a plurality of virtual segments, at least said second storage apparatus is configured to have a pool composed of a plurality of real pages, each storage apparatus is configured to manage a virtual pool comprising one or more pools including at least said pool, said virtual pool is composed of a plurality of virtual pages, each virtual page corresponding to any real page, and said first storage apparatus is configured to receive a write command that specifies an address belonging to an unallocated virtual segment, allocate a free virtual page to said unallocated virtual segment, and write data to the real page corresponding to the allocated virtual page, even when said first storage apparatus does not have a pool composed of real pages.

Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated.

Abstract: A system on chip (SoC) including a memory management unit (MMU) and a memory address translation method thereof are provided. The SoC includes a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets; an MMU module comprising a plurality of MMUs, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request, on which address translation has been performed in at least one of the MMUs, to the memory device; and a second bus interconnect configured to connect the master IP with the MMU module and to allocate one of the MMUs for each of the working sets.

Abstract: A semiconductor memory storage apparatus includes a packetization unit receiving content data includes a plurality of variable-length frames, and adding management data showing frame data inherent information to frame data of each variable-length frame, and further, packetizing the content data storing the frame data and the management data in each fixed-length packet for every variable-length frame, a buffer temporarily storing the content data at a fixed-length packet unit in write/read operation of the content data packetized at the fixed-length packet unit, a storage unit using a non-volatile memory as an information storage medium, and storing the content data supplied from the buffer, and a controller writing/reading content data packetized at the fixed-length packet unit with respect to the storage unit at a fixed-length packet unit.

Abstract: System and method for operating a solid state memory containing a memory space. The present invention provides a computerized system that includes a solid state memory having a memory space; a controller adapted to use a first portion of the memory space as a cache; and a garbage collector adapted to use a second portion of the memory space to collect garbage in the solid state memory. The controller is adapted to change a size of at least one of the first portion and the second portion of the memory space during operation of the solid state memory.

Abstract: An electronic apparatus that includes a controlled device with a plurality of control registers. A data bus is coupled between the controlled device and a processor, and an interface is configured to receive a plurality of portions of data read from or to be written to the plurality of control registers. The electronic apparatus also includes a correlation circuit configured to associate at least some of the plurality of portions of data with respective physical addresses of the plurality of control registers based on respective positions of the respective portions of data within the plurality.