Abstract: A solid-state imaging element of an embodiment of the present disclosure includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel transistor provided on one surface of the semiconductor substrate; and an element separation section provided in the semiconductor substrate and including a first element separation section and a second element separation section that have mutually different configurations, the element separation section defining an active region of the pixel transistor, in which the second element separation section has, on a side surface, a first semiconductor region and a second semiconductor region that have mutually different impurity concentrations in a depth direction of the second element separation section.

Abstract: A method includes positioning a discrete component assembly on a support fixture of a component transfer system, the discrete component assembly including a dynamic release tape including a flexible support layer, and a dynamic release structure disposed on the flexible support layer, and a discrete component adhered to the dynamic release tape. The method includes irradiating the dynamic release structure to release the discrete component from the dynamic release tape.

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.

Abstract: A detection device includes a substrate, a plurality of detection electrodes arranged in a detection area of the substrate, an organic semiconductor layer that covers the detection electrodes, and a counter electrode provided above the organic semiconductor layer. The organic semiconductor layer includes at least either of a first p-type semiconductor layer and a first n-type semiconductor layer, and an active layer. The active layer is provided in each overlapping area overlapping a corresponding one of the detection electrodes, and has a structure in which a p-type semiconductor area and an n-type semiconductor area are mixed and coexist. The first p-type semiconductor layer or the first n-type semiconductor layer is provided in a non-overlapping area not overlapping the detection electrode, and is provided between the adjacent active layers.

Abstract: A poling apparatus for poling a polymer thin film formed on a workpiece carried by a workpiece carrier. The workpiece has grounding electrodes and grounding pads located at edges, and a thin film covering the grounding electrodes but exposing the grounding pads. The workpiece carrier has carrier electrodes located around the workpiece and inside grounding ports at the bottom. The poling apparatus includes, in a poling chamber, a poling source generating a plasma, a Z-elevator to raise the workpiece carrier toward the poling source using the grounding ports, and grounding mechanisms including downwardly biased electrical contacts which, when the workpiece carrier is raised by the Z-elevator, connect the grounding pads of the workpiece with the carrier electrodes, to ground the workpiece. The poling apparatus additionally includes preparation platform and transfer platform with conveyer systems with rollers and Z-elevators to move the workpiece carrier in and out of the poling chamber.

Abstract: The present disclosure provides an optical-sensing device, a manufacturing method thereof, and a display panel. The optical-sensing device includes a sensor TFT disposed on a substrate and a switch TFT connected with the sensor TFT. The sensor TFT and the switch TFT include a first active layer and a second active layer, the first active layer comprises a first IGZO layer and a perovskite layer disposed on the first IGZO layer, and the second active layer comprises a second IGZO layer.

Abstract: To increase the capacity of a charge holding section of a pixel in an imaging device that performs imaging using a global shutter method. An imaging device includes a photoelectric converter, a first charge holding section, an auxiliary charge holding section, a transfer route, and an image signal generator. The first charge holding section is formed near a front surface of a semiconductor substrate. A first charge transfer section transfers charge from the photoelectric converter to the first charge holding section. The auxiliary charge holding section underlies the first charge holding section, and holds a portion of the charges held in the first charge holding section. The transfer route transfers the charge between the first charge holding section and the auxiliary charge holding section. The image signal generator generates an image signal based on the charges held in the first charge holding section and the auxiliary charge holding section.

Abstract: An apparatus and an operating method for automated wafer carrier handling are provided. The operation method includes bring a base frame and an engaging mechanism of an automated wafer carrier handling apparatus into abutting contact with a top flange mounted on a wafer carrier to limit at least one degree of freedom of movement of the top flange, where the engaging mechanism is disposed on the base frame; transporting the wafer carrier to a destination location by the automated wafer carrier handling apparatus; and releasing the top flange mounted on the wafer carrier from the automated wafer carrier handling apparatus at the destination location.

Abstract: According to one embodiment, an isolator includes first and second electrodes, first and second insulating portions, and a first dielectric portion. The first insulating portion is provided on the first electrode. The second electrode is provided on the first insulating portion. The second insulating portion is provided around the second electrode along a first plane perpendicular to a first direction. The second insulating portion contacts the second electrode. The first dielectric portion is provided between the first and second insulating portions. At least a portion of the first dielectric portion contacts the second electrode and is positioned around the second electrode along the first plane. A distance between a lower end of the second electrode and a first interface between the first dielectric portion and the second insulating portion is less than a distance between the first interface and an upper end of the second electrode.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.

Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. Different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nano structure (e.g., nanosheet, nanowire, or the like) GAA devices. A GAA device may be formed with a vertical stack of nanostructures in a channel region with a topmost nanostructure of the vertical stack being thicker than the other nanostructures of the vertical stack. Furthermore, an LDD portion of the topmost nano structure may be formed as the thickest of the nanostructures in the vertical stack.

Abstract: Methods, devices, and systems are described for performing quantum operations. An example device at least one magnetic field source configured to supply an inhomogeneous magnetic field, at least one semiconducting layer, and one or more conducting layers configured to: define at least two quantum states in the at least one semiconducting layer, and cause, based on an oscillating electrical signal supplied by the one or more conducting layers, an electron to move back and forth between the at least two quantum states in the presence of the inhomogeneous magnetic field. The movement of the electron between the at least two quantum states may generate an oscillating magnetic field to drive a quantum transition between a spin-up state and spin-down state of the electron thereby implementing a qubit gate on a spin state of the electron.

Abstract: Embodiments disclosed herein include a method of determining the position of a sensor wafer relative to a pedestal. In an embodiment, the method comprises placing a sensor wafer onto the pedestal, wherein the sensor wafer comprises a first surface that is supported by the pedestal, a second surface opposite the first surface, and an edge surface connecting the first surface to the second surface, wherein a plurality of sensor regions are formed on the edge surface, and wherein the pedestal comprises a major surface and an annular wall surrounding the sensor wafer. In an embodiment, the method further comprises determining a gap distance between each of the plurality of sensor regions and the annular wall. In an embodiment, the method may further comprise determining a center-point offset of a center-point of the sensor wafer relative to a center point of the annular wall from the gap distances.

Abstract: Examples of a semiconductor device includes a transistor region formed in a semiconductor substrate having a first conductivity type drift layer, and a diode region formed to be adjacent to the transistor region in the semiconductor substrate, wherein the diode region has a second conductivity type anode layer formed on the drift layer and a first conductivity type cathode layer formed on the lower side of the drift layer, and the cathode layer has an adjacent region contacting the transistor region, the adjacent region having a depth, from a lower surface of the semiconductor substrate, which becomes shallower toward the transistor region and having first conductivity type impurity concentration which decreases toward the transistor region.

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

Abstract: There is provided a method of processing a wafer having devices formed in respective areas on a face side thereof that are demarcated by a plurality of crossing projected dicing lines on the face side. The method of processing a wafer includes a wafer unit forming step of forming a wafer unit having a wafer, a tape, and an annular frame, a dividing step of dividing the wafer along the projected dicing lines into a plurality of device chips, a pick-up step of picking up one at a time of the device chips from the wafer unit, and a measuring step of measuring the device chip picked up in the pick-up step. The method also includes a distinguishing step, before the pick-up step, of inspecting properties of the devices to distinguish acceptable devices and defective devices among the devices and storing distinguished results.

Abstract: A semiconductor wafer transport apparatus having a transport arm and at least one end effector. An optical edge detection sensor is coupled to the transport arm and is configured so as to register and effect edge detection of a wafer supported by the end effector. An illumination source illuminates a surface of the wafer and is disposed with respect to the optical edge detection sensor so that the surface directs reflected surface illumination, from the illumination source, toward the optical edge detection sensor, and optically blanks, at the peripheral edge of the wafer, background reflection light of a background, viewed by the optical edge detection sensor coincident with linear traverse of the wafer supported by the at least one end effector. The peripheral edge of the wafer is defined in relief in image contrast to effect edge detection coincident with traverse of the wafer supported by the end effector.

Abstract: Disclosed are various embodiments for a piezo-composite transducer that is flexible such that it may conform to regular or irregular shapes. A flexible piezo-composite transducer may include an active piezoelectric material, such as PZT-5H, and a passive polymer matrix formed of a flexible material, such as polydimethylsiloxane (PDMS). The flexible piezo-composite transducer may include a first side and a second side, where each of the first side and the second side include a first electrode and a second electrode deposited thereon, respectively. At least one of the first electrode and the second electrode may include a silver nanowire (AgNW) and PDMS electrode that is flexible.

Abstract: Examples of a semiconductor device includes a transistor region formed in a semiconductor substrate having a first conductivity type drift layer, and a diode region formed to be adjacent to the transistor region in the semiconductor substrate, wherein the diode region has a second conductivity type anode layer formed on the drift layer and a first conductivity type cathode layer formed on the lower side of the drift layer, and the cathode layer has an adjacent region contacting the transistor region, the adjacent region having a depth, from a lower surface of the semiconductor substrate, which becomes shallower toward the transistor region and having first conductivity type impurity concentration which decreases toward the transistor region.