Patents Examined by Jarrett J. Stark
  • Patent number: 10734507
    Abstract: A semiconductor device includes a first IGBT cell having a second-type doped drift zone and a desaturation semiconductor structure for desaturating a charge carrier concentration in the first IGBT cell. The desaturation semiconductor structure includes a first-type doped region forming a pn-junction with the drift zone and two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction. The two trenches confine a mesa region including a first-type doped desaturation channel region and a first-type doped body region at least in the lateral direction. The desaturation channel region and the body region adjoin each other, and the desaturation channel region is a depletable region. Related methods of manufacture are also described.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze
  • Patent number: 10734513
    Abstract: Heterojunction tunnel field effect transistors (hTFETs) incorporating one or more oxide semiconductor and a band offset between at least one of a channel material, a source material of a first conductivity type, and drain of a second conductivity type, complementary to the first. In some embodiments, at least one of p-type material, channel material and n-type material comprises an oxide semiconductor. In some embodiments, two or more of p-type material, channel material, and n-type material comprises an oxide semiconductor. In some n-type hTFET embodiments, all of p-type, channel, and n-type materials are oxide semiconductors with a type-II or type-III band offset between the p-type and channel material.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Jack T. Kavalieros, Elijah V. Karpov, Uday Shah, Ravi Pillarisetty
  • Patent number: 10727307
    Abstract: A display substrate and a fabrication method thereof, and a display device are disclosed. The fabrication method of a display substrate, includes forming a first gate electrode on a transparent base substrate; forming a transparent gate insulating layer on the first gate electrode; forming a transparent active layer on the transparent gate insulating layer; forming a transparent source electrode and a transparent drain electrode on the transparent active layer, wherein, the transparent source electrode and the transparent drain electrode do not overlap with the first gate electrode in a thickness direction of the transparent base substrate.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: July 28, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xiaming Zhu
  • Patent number: 10727325
    Abstract: A horizontal vacuum channel transistor is provided. The horizontal transistor includes a substrate, horizontal emitter and collector electrodes formed in a layer of semiconductor material of the substrate, and a horizontal insulated gate located between the emitter and collector electrodes. The emitter electrode includes multiple horizontally-aligned emitter tips connected to a planar common portion, and the collector electrode includes a planar portion. The gate includes multiple horizontally-aligned gate apertures passing through the gate that each correspond to one of the emitter tips of the emitter electrode. The minimum distance between the emitter and collector electrodes is less than about 180 nm. Also provided are a vertical vacuum channel transistor having vertically-stacked emitter and collector electrodes, and methods for fabricating vacuum channel transistors.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 28, 2020
    Assignee: United States of America as Represented by the Administrator of NASA
    Inventors: Jin-Woo Han, Meyya Meyyappan
  • Patent number: 10720330
    Abstract: A semiconductor device includes: a first-conductivity-type drift layer including a first-conductivity-type impurity, vacancy-oxygen-hydrogen complex defects each caused by a vacancy, an oxygen atom, and a hydrogen atom, divacancy-and-vacancy-phosphorus complex defects, having a trap density level lower than a trap density level of the vacancy-oxygen-hydrogen complex defect, and third complex defects; a plurality of donor layers provided at different depths in a depth direction of the first-conductivity-type drift layer, wherein each of the plurality of donor layers includes donors caused by the vacancy-oxygen-hydrogen complex defects, and each of the plurality of donor layers has an impurity concentration distribution that includes a first portion with a maximum impurity concentration and a second portion with a concentration gradient in which the impurity concentration is reduced from the first portion to both main surfaces of the first-conductivity-type drift layer; and a second-conductivity-type semiconduc
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tomonori Mizushima, Yusuke Kobayashi
  • Patent number: 10707344
    Abstract: A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Furen Lin, Frank Baiocchi, Yunlong Liu, Lark Liu, Tianping Lv, Peter Lin, Ho Lin
  • Patent number: 10700061
    Abstract: A semiconductor device includes a first transistor and a second transistor in a semiconductor substrate. The first transistor includes a first drain contact electrically connected to a first drain region, the first drain contact including a first drain contact portion and a second drain contact portion. The first drain contact portion includes a drain conductive material in direct contact with the first drain region. The second transistor includes a second source contact electrically connected to a second source region. The second source contact includes a first source contact portion and a second source contact portion. The first source contact portion includes a source conductive material in direct contact with the second source region.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Dirk Ahlers, Till Schloesser
  • Patent number: 10693008
    Abstract: An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Marko Radosavljevic, Jack T. Kavalieros, Ravi Pillarisetty, Niti Goel, Van H. Le, Gilbert Dewey, Benjamin Chu-Kung
  • Patent number: 10693063
    Abstract: A semiconductor device includes memory cells, a first dielectric liner material overlying side surfaces of the memory cells, a high-k dielectric material overlying side surfaces of the first dielectric liner material, a second dielectric liner material overlying side surfaces of the high-k dielectric material, and an additional dielectric material overlying side surfaces of the second dielectric liner material. A memory structure, an electronic system, and a method of forming a memory structure are also described.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Andrew J. Hansen, James A. Cultra
  • Patent number: 10692793
    Abstract: A semiconductor device includes a substrate; a die attached to the substrate; an encapsulation covering the substrate and the die, wherein the die is embedded within the encapsulation; and a heating element embedded within the encapsulation, wherein the heating element is configured to provide thermal energy to the die.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Patent number: 10686035
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: June 16, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Patent number: 10680430
    Abstract: Methods and systems for self-healing fault recovery in an electrical power distribution network, particularly distribution networks employing a mesh configuration. When a power source circuit breaker is tripped one or more virtual paths is traced throughout the mesh network, each virtual path originating at the power source that is offline, terminating at an alternate power source, and containing one or two open load switches. A restoration path is chosen from the virtual paths. Power can be transferred to other segments of the mesh network by isolating the fault and closing the open load switch in the chosen restoration path. Some or all of the method and system can be automated.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 9, 2020
    Assignees: TIKLA COM INC., MESHED POWER SYSTEMS INC.
    Inventor: Eduardo Chaiquin
  • Patent number: 10672867
    Abstract: A method includes forming a fin structure over a substrate; forming an isolation structure around the fin structure; etching the fin structure to form a recess in the fin structure; epitaxially growing a source drain structure in the recess; depositing a capping layer over a first portion of the source drain structure, in which the first portion of the source drain structure is over the isolation structure; recessing the isolation structure to expose a second portion of the source drain structure; and etching the second portion of the source drain structure, in which the first portion of the source drain structure remains over the isolation structure after etching the second portion of the source drain structure.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tai-Yuan Wang
  • Patent number: 10665601
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first and second vertical conductive patterns isolated from each other by a first slit. The semiconductor device may include at least one first half conductive pattern extending toward a first region disposed at one side of the first slit from the first vertical conductive pattern. The semiconductor device may include at least one second half conductive pattern extending toward a second region disposed at the other side of the first slit from the second vertical conductive pattern.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10665723
    Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Min Song, Woo Seok Park, Geum Jong Bae, Dong Il Bae, Jung Gil Yang
  • Patent number: 10658337
    Abstract: Packages and packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a molding compound and a plurality of through-vias disposed in the molding compound. The package includes an interconnect structure disposed over the plurality of through-vias and the molding compound. The interconnect structure includes a metallization layer. The metallization layer includes a plurality of contact pads and a fuse.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Hsien-Wei Chen, Der-Chyang Yeh, An-Jhih Su
  • Patent number: 10651189
    Abstract: A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. A stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: May 12, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10651645
    Abstract: Systems and methods for fault detection and protection in electric power systems that evaluates electromagnetic transients caused by faults. A fault can be detected using sampled data from a first monitored point in the power system. Detection of fault transients and associated characteristics, including transient direction, can also be extracted through evaluation of sample data from other monitored points in the power system. A monitoring device can evaluate whether to trip a switching device in response to the detection of the fault and based on confirmation of an indication of detection of fault transients at the other monitored points of the power system. The determination of whether to trip or activate the switching device can also be based on other factors, including the timing of receipt of an indication of the detection of the fault transients and/or an evaluation of the characteristics of the detected transients.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: May 12, 2020
    Assignee: ABB Inc.
    Inventors: Tao Cui, Reynaldo Nuqui, Dmitry Ishchenko, Zhenyuan Wang
  • Patent number: 10641553
    Abstract: The controller receives information including a plurality of evaluation indexes, a weight of each evaluation index, the number of times for calculating a value of an evaluation function, and initial parameter values, and performs a simulation based on the received information. Then, the controller calculates a value of an evaluation function based on a result of the simulation, and determines whether the calculated value of the evaluation function is minimum, to update parameters when it is determined that the value of the evaluation function is minimum. In the calculation of a value of the evaluation function, a value of the evaluation function is calculated again based on the number of times for calculating a value of an evaluation function. The controller generates new parameters by a genetic algorithm when a value of an evaluation function is calculated again.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: May 5, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Yuto Noda, Tatsuya Yamaguchi, Masayoshi Masunaga, Koji Yoshii
  • Patent number: 10636940
    Abstract: A semiconductor light-emitting device includes a light-emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, and a magnetic layer on the light-emitting structure. The magnetic layer may have at least one magnetization direction that is parallel to an upper surface of the active layer. The magnetic layer may generate a magnetic field that is parallel to the upper surface of the active layer. The magnetic layer may include multiple structures that may have different magnetization directions. Multiple magnetic layers may be included on the light-emitting structure. A magnetic layer may be on a contact electrode. A magnetic layer may be isolated from a pad electrode.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan Tae Lim, Yong Il Kim, Nam Goo Cha, Sung Hyun Sim