Patents Examined by Jarrett J. Stark
  • Patent number: 11121242
    Abstract: A method is provided for operating a semiconductor device which includes an IGBT having a desaturation semiconductor structure connected to a first electrode terminal and a gate electrode terminal for controlling a desaturation channel. The method includes: applying a first gate voltage to the gate electrode terminal so that current flows through the IGBT between the first electrode terminal and a second electrode terminal and current flow through the desaturation channel is substantially blocked; applying a different second gate voltage to the gate electrode terminal so that current flows through the IGBT between the first and second electrode terminals and charge carriers flow as a desaturating current through the desaturation channel to the first electrode terminal; and applying a different third gate voltage to the gate electrode terminal so that current flow through the IGBT between the first and second electrode terminals is substantially blocked.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: September 14, 2021
    Assignee: Infineon Technologies AG
    Inventors: Johannes Laven, Hans-Joachim Schulze
  • Patent number: 11121025
    Abstract: A method of manufacturing a semiconductor device includes etching a via through a dielectric layer and an etch stop layer (ESL) to a source/drain contact, forming a recess in the top surface of the source/drain contact such that the top surface of the source/drain contact is concave, and forming an oxide liner on the sidewalls of the via. The oxide liner traps impurities left behind by the etching of the via through the dielectric layer and the ESL, wherein the etching, the forming the recess, and the forming the oxide liner are performed in a first chamber. The method further includes performing a pre-cleaning that removes the oxide liner and depositing a metal in the via.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Chang Hsu, Sheng-Liang Pan, Huan-Just Lin, Jack Kuo-Ping Kuo
  • Patent number: 11114452
    Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
  • Patent number: 11114496
    Abstract: An active matrix substrate includes: a photoelectric conversion element 15; an electrode 14b provided with a first opening h1 and disposed on one surface of the photoelectric conversion element 15; an organic insulating film 106 provided with a second opening h2 and covering the photoelectric conversion element 15 and the electrode 14b; and a conductive film 16 for supplying a bias voltage to the electrode 14b. The first opening h1 and the second opening h2 overlap each other when viewed in plan view. The conductive film 16 is provided inside the first opening h1 and the second opening h2 so as to be in contact with the electrode 14b.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: September 7, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Makoto Nakazawa
  • Patent number: 11108002
    Abstract: When visible light (light having wavelength of 380 nm or more and 780 nm or less) is transmitted through a first light transmitting region (TR1) (a first light emitting portion (160a)), a second light transmitting region (TR2) (a second light emitting portion (160b)) and a third light transmitting region (TR3) (a first light transmitting portion (162)), more specifically, when light from a D65 light source is transmitted through the first light transmitting region (TR1), the second light transmitting region (TR2) and the third light transmitting region (TR3), both of a color difference between the first light transmitting region (TR1) and the third light transmitting region (TR3) and a color difference between the second light transmitting region (TR2) and the third light transmitting region (TR3) are both, for example, 0.4 or more and 6.5 or less in CIELAB. This reduces conspicuousness of both of the first light transmitting region (TR1) and the second light transmitting region (TR2).
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: August 31, 2021
    Assignees: PIONEER CORPORATION, TOHOKU PIONEER CORPORATION
    Inventor: Noriaki Waki
  • Patent number: 11101175
    Abstract: Chamferless via structures and methods of manufacture are provided. The structures include a conductive line and a set of chamferless wiring vias formed in a dielectric material with at least one of the vias in contact with the conductive line. The set of chamferless wiring vias is formed with at least a first subset of wiring vias of a first height and a second subset of wiring vias of a second height. The method includes filling trenches within a substrate with a conductive material to form a set of wiring vias with a first height. Next, a block mask is used over a capping material layer to expose a portion of the conductive material layer. The capping material and the conductive material of the set of wiring vias defined by the block mask are etched forming a subset of wiring vias of the second height.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Chih-Chao Yang, Hosadurga Shobha
  • Patent number: 11101367
    Abstract: A method for forming a device structure provides for forming a fin of a semiconductor material. A first contact is formed on the fin. A second contact is formed on the fin and spaced along a length of the fin from the first contact. A self-aligned gate electrode is formed on the fin that is positioned along the length of the fin between the first contact and the second contact.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Terence B. Hook, Myung-Hee Na, Balasubramanian Pranatharthiharan, Andreas Scholze
  • Patent number: 11081396
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: 11075251
    Abstract: A flexible display device includes a protection member, a first adhesion member, a display member, a second adhesion member, and a window member. A thickness of the display member is less than a sum of thicknesses of the protection member and the window member. The display member includes a display panel layer, a touch sensing layer, and a reflection prevention layer integrated with each other to reduce a thickness of the flexible display device. The reduction in thickness enables the flexible display device to be bent with a relatively small radius of curvature, as well as to be repeatedly bent (or otherwise flexed) with reduced potential for delamination of the first and second adhesion members.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: July 27, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Taehoon Yang, Yongsu Lee, Sungchul Kim, Sunghoon Kim, Sungsik Yun, Kyoungah Lee
  • Patent number: 11075262
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a semiconductor member, and a first crystal member. A direction from the first electrode toward the second electrode is aligned with a first direction. A position in the first direction of the third electrode is between positions in the first direction of the first electrode and the second electrode. The semiconductor member includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The semiconductor member includes a first region, and first and second partial regions. The first region is between the first and second electrodes in the first direction. A second direction from the first region toward the third electrode crosses the first direction. The first crystal member is provided between the first and third electrodes in the second direction.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: July 27, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeya Kimura, Hisashi Yoshida, Tatsuo Shimizu, Ryosuke Iijima
  • Patent number: 11074951
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistive element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The first magnetic layer contains nickel (Ni), cobalt (Co), manganese (Mn) and gallium (Ga) and has a spin polarization less than 0.71.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tatsuya Kishi
  • Patent number: 11069850
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a fixed magnetization direction, a nonmagnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the nonmagnetic layer and having a variable magnetization direction, a first insulating layer provided along a side surface of the stacked structure and having an upper end located at a position lower than an upper end of the side surface of the stacked structure, and a second insulating layer covering the first insulating layer and having an upper end located at a position higher than the upper end of the first insulating layer.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshinori Kumura
  • Patent number: 11050043
    Abstract: A display device includes a light emitting element layer and a light scattering layer disposed on the light emitting element layer. The light scattering layer may include a low refractive part that includes a plurality of protruding portions and a high refractive part that covers the protruding portions.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: June 29, 2021
    Inventors: Byeong-kwon Ju, Youngwook Park, Cheolhwee Park, Youngtak Lee, Jinwoo Park
  • Patent number: 11024488
    Abstract: In a film-forming technology using charged particles, a disturbance in film thickness distribution caused by leakage magnetic field is suppressed. A film-forming method embodies a technological idea of switching generation and stop of a magnetic field during a film-forming operation so as to stop the generation of the magnetic field during a period when plasma is generated and generate the magnetic field during a period when plasma is not generated.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 1, 2021
    Assignee: THE JAPAN STEEL WORKS, LTD.
    Inventors: Keisuke Washio, Masao Nakata, Tatsuya Matsumoto, Junichi Shida
  • Patent number: 11024611
    Abstract: A micro-LED transfer method, manufacturing method and display device are provided. The micro-LED transfer method comprises: bonding the micro-LED array on a first substrate onto a receiving substrate through micro-bumps, wherein the first substrate is laser transparent; applying underfill into a gap between the first substrate and the receiving substrate; irradiating laser onto the micro-LED array from a side of the first substrate to lift-off the micro-LED array from the first substrate; and removing the underfill.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 1, 2021
    Assignee: Goertek, Inc.
    Inventors: Quanbo Zou, Peixuan Chen, Xiangxu Feng, Tao Gan, Xiaoyang Zhang, Zhe Wang
  • Patent number: 11018272
    Abstract: A method for concurrently forming a first metal electrode (31, 58) on an n-type region of a silicon substrate (10) and a second metal electrode (32, 59) on a p-type region of the silicon substrate, wherein the n-type region and the p-type region are respectively exposed in a first and in a second area, is disclosed. The method comprises: depositing (101) an initial metal layer comprising Ni (33, 53) simultaneously in the first area and in the second area by a Ni immersion plating process using a plating solution; and depositing (102) a further metal layer (34, 54) on the initial metal layer comprising Ni (33, 53) in the first area and in the second area by an electroless metal plating process or by an immersion metal plating process, wherein the plating solution comprises Ni and a predetermined amount of another metal different from Ni.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 25, 2021
    Assignee: IMEC VZW
    Inventor: Richard Russell
  • Patent number: 11014804
    Abstract: Systems and methods for fabricating 3D soft microstructures. The system comprises injecting a pressurized, curable liquid into certain structural layers induces folding and allows the 2D structures to reconfigure into a 3D form In addition to the injection of a curable liquid that permanently reconfigures the structure of the system, in an embodiment this method also allows for the injection of other liquids into certain actuator layers that enable motion in certain portions of the system Furthermore, the system allows for handling of colored fluids that are passed to visualization layers. The method of creating such a system depends on taking advantage of laser machining of the individual layers to influence the behavior of how different portions bend and move.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: May 25, 2021
    Assignee: President and Fellows of Harvard College
    Inventors: Nicholas W. Bartlett, Tommaso Ranzani, Sheila Russo, Conor J. Walsh, Michael Wehner, Robert J. Wood
  • Patent number: 11011693
    Abstract: Embodiments of the present disclosure describe integrated quantum circuit assemblies that include quantum circuit components pre-packaged, or integrated, with some other electronic components and mechanical attachment means for easy inclusion within a cooling apparatus. An example integrated quantum circuit assembly includes a package and mechanical attachment means for securing the package within a cryogenic chamber of a cooling apparatus. The package includes a plurality of components, such as a quantum circuit component, an attenuator, and a directional coupler, which are integral to the package. Such an integrated assembly may significantly speed up installation and may help develop systems for rapidly bringing up quantum computers.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Lester Lampert, Ravi Pillarisetty, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, David J. Michalak, Roman Caudillo, Thomas Francis Watson, Stephanie A. Bojarski, James S. Clarke
  • Patent number: 11011538
    Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Luan C. Tran, Jie Li, Anish A. Khandekar, Kunal Shrotri
  • Patent number: 11011543
    Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: May 18, 2021
    Inventors: Joon-Sung Lim, Jang-Gn YuN, Jaesun Yun