Patents Examined by Jarrett J. Stark
  • Patent number: 11462417
    Abstract: Disclosed herein is an apparatus and method for annealing semiconductor substrates. In one example a temperature-controlled fluid circuit includes a condenser configured to fluidly connect to an internal volume of a processing chamber. The processing chamber has a body, the internal volume is within the body. The condenser is configured to condense a processing fluid into liquid phase. A source conduit includes a first terminal end that couples to a first port on the body of the processing chamber. The source conduit includes a second terminal end. The first terminal end couples to a gas panel. The gas panel is configured to provide a processing fluid into the internal volume of the processing chamber. A gas conduit includes a first end. The first end couples to the condenser and a second end. The second end is configured to couple to a second port on the body of the processing chamber.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: October 4, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jean Delmas, Steven Verhaverbeke, Kurtis Leschkies
  • Patent number: 11450706
    Abstract: A structural body includes a first dielectric layer and a second dielectric layer which is in contact with the first dielectric layer and which has a refractive index different from that of the first dielectric layer. The second dielectric layer includes at least two dielectric films different in hydrogen concentration from each other. The interface between the first dielectric layer and the second dielectric layer has periodic first irregularities.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: September 20, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kosaku Saeki, Seiji Nishiwaki, Kenji Narumi
  • Patent number: 11450757
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Grant
    Filed: September 6, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li, Tien-Shun Chang
  • Patent number: 11444059
    Abstract: A stacked die structure for a semiconductor device generally includes a primary level with a first die formed in a wafer, and a second level with a second die coupled to the first die. A third level includes a third die coupled to the second die. The levels have conductive first, second, and third interconnects, respectively, extending from active sides of the dies and may be bonded prior to stacking the dies. The dies may be stacked in an offset or rotated position relative to each other such that the interconnects extend beyond each of the other dies to contact a redistribution layer that forms electrical connections with external components. In some configurations, a fourth level having a fourth die and a conductive fourth interconnect is coupled to the third die and positioned laterally offset from the third die such that the third interconnect extends beyond the fourth die.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Chih Yuan Chang
  • Patent number: 11444148
    Abstract: An inductor is disclosed. The inductor includes a vertically coiled conductor, a metal contact coupled to a first end of the vertically coiled conductor, and a dielectric material coupled to the metal contact. A tunable high permittivity component is coupled to a second end of the vertically coiled conductor.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Gwang-Soo Kim, Aaron D. Lilak, Kumhyo Byon, Doug Ingerly
  • Patent number: 11436516
    Abstract: A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 6, 2022
    Assignee: Google LLC
    Inventors: Julian Shaw Kelly, Joshua Yousouf Mutus
  • Patent number: 11437262
    Abstract: Methods and systems of detection of wafer de-chucking in a semiconductor processing chamber are disclosed. Methods and systems of interdiction are also disclosed to prevent hardware and wafer damage during semiconductor fabrication if and when de-chucking is detected. In one embodiment, a de-chucking detection method is based on measuring change in imaginary impedance of a plasma circuit, along with measuring one or both of reflected RF power and arc count. In another embodiment, a possibility of imminent de-chucking is detected even before complete de-chucking occurs by analyzing the signature change in imaginary impedance.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 6, 2022
    Assignee: Applied Materials, Inc
    Inventors: Ganesh Balasubramanian, Byung Chul Yoon, Hemant Mungekar
  • Patent number: 11437347
    Abstract: A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 6, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chen-Liang Ma, Zih-Song Wang
  • Patent number: 11417801
    Abstract: A micro light-emitting diode (LED) includes an epitaxial layered structure including a support layer, a first-type semiconductor element, an active layer, and a second-type semiconductor element that are sequentially disposed on one another in such order. A method for manufacturing a micro LED device including at least one of the micro LED is also disclosed.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 16, 2022
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Cuicui Sheng, Chun Kai Huang, Chun-Yi Wu
  • Patent number: 11411036
    Abstract: A solid-state imaging device includes a first substrate including a first semiconductor substrate and a first multi-layered wiring layer stacked on the first semiconductor substrate, a second substrate including a second semiconductor substrate and a second multi-layered wiring layer stacked on the second semiconductor substrate, a third substrate including a third semiconductor substrate and a third multi-layered wiring layer stacked on the third semiconductor substrate, and a first coupling structure for electrically coupling the first substrate and the second substrate. The first substrate, the second substrate, and the third substrate are stacked in this order. The first substrate and the second substrate are bonded together such that the first multi-layered wiring layer and the second multi-layered wiring layer are opposed to each other. The first substrate excludes a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 9, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
  • Patent number: 11404296
    Abstract: Embodiments disclosed herein include a method of determining the position of a sensor wafer relative to a pedestal. In an embodiment, the method comprises placing a sensor wafer onto the pedestal, wherein the sensor wafer comprises a first surface that is supported by the pedestal, a second surface opposite the first surface, and an edge surface connecting the first surface to the second surface, wherein a plurality of sensor regions are formed on the edge surface, and wherein the pedestal comprises a major surface and an annular wall surrounding the sensor wafer. In an embodiment, the method further comprises determining a gap distance between each of the plurality of sensor regions and the annular wall. In an embodiment, the method may further comprise determining a center-point offset of a center-point of the sensor wafer relative to a center point of the annular wall from the gap distances.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: August 2, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Charles G. Potter, Anthony D. Vaughan
  • Patent number: 11404405
    Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: August 2, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Titash Rakshit, Borna J. Obradovic, Chris Bowen, Mark S. Rodder
  • Patent number: 11398563
    Abstract: Examples of a semiconductor device includes a transistor region formed in a semiconductor substrate having a first conductivity type drift layer, and a diode region formed to be adjacent to the transistor region in the semiconductor substrate, wherein the diode region has a second conductivity type anode layer formed on the drift layer and a first conductivity type cathode layer formed on the lower side of the drift layer, and the cathode layer has an adjacent region contacting the transistor region, the adjacent region having a depth, from a lower surface of the semiconductor substrate, which becomes shallower toward the transistor region and having first conductivity type impurity concentration which decreases toward the transistor region.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 26, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryu Kamibaba, Tetsuo Takahashi, Akihiko Furukawa
  • Patent number: 11398392
    Abstract: An integrated circuit (IC) device includes a lower electrode including a main portion having a sidewall with at least one step portion, and a top portion having a width less than that of the main portion in a lateral direction. An upper support pattern contacts the top portion of the lower electrode. The upper support pattern includes a seam portion. To manufacture an IC device, a mold pattern and an upper sacrificial support pattern through which a plurality of holes pass are formed on a substrate. A plurality of lower electrodes are formed inside the plurality of holes. A peripheral space is formed on the mold pattern. An enlarged peripheral space is formed by reducing a width and a height of the top portion. An upper support pattern is formed to fill the enlarged peripheral space.
    Type: Grant
    Filed: May 24, 2020
    Date of Patent: July 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoungdeog Choi, Dongyoung Kim
  • Patent number: 11393861
    Abstract: A flare-suppressing image sensor includes a first pixel formed in a substrate and a refractive element located above the first pixel. The refractive element has, with respect to a top surface of the substrate, a height profile having at least two one-dimensional local maxima in each of a first cross-sectional plane and a second cross-sectional plane perpendicular to the first cross-sectional plane. Each of the first and second cross-sectional planes is perpendicular to the top surface and intersects the first pixel.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: July 19, 2022
    Assignee: OmniVision Technologies, Inc.
    Inventors: Alireza Bonakdar, Zhiqiang Lin, Chen-Wei Lu
  • Patent number: 11393855
    Abstract: A photoelectric conversion apparatus includes a first semiconductor region of a first conductivity type at a first depth from a first surface, a second semiconductor region of a second conductivity type disposed at a second depth deeper than the first depth from the first surface so as to be in contact with the first semiconductor region, and a third semiconductor region of the second conductivity type extending from the first surface to a third depth shallower than the second depth and being in contact with the first semiconductor region and the second semiconductor region. The third semiconductor region has a higher impurity concentration than the second semiconductor region. A second electric potential lower than the first electric potential for a carrier of the first conductivity type is applied to the third semiconductor region. The second semiconductor region has an impurity concentration of 1×1012 [atom/cm3] or less.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: July 19, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hajime Ikeda, Yusuke Onuki
  • Patent number: 11387290
    Abstract: A photodetector (300) includes a first electrode (313) and a second electrode (314) on a base substrate (100); a light-sensitive layer (311) between the first electrode (313) and the second electrode (314); and a light-trapping layer (312) between the light-sensitive layer (311) and the base substrate (100), wherein a surface of the light-trapping layer (312) opposite from the base substrate (100) comprises a plurality of first recessed portions.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: July 12, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Guoqiang Wang
  • Patent number: 11387129
    Abstract: A substrate warehouse stores a container housing a substrate, and includes a transfer-in part which allows the container to be mounted thereon when the container is transferred-in from an outside; a transfer-out part which allows the container to be mounted thereon when the container is transferred-out to the outside; and a standby part which allows the container standing by for transfer-out to the outside to be mounted thereon. Also included is a functional part including an inspection that performs processing of inspecting the substrate; a delivery part which allows the container to be mounted thereon when delivering the substrate between the functional part and the container; a container transfer mechanism which transfers the container in the substrate warehouse; and a substrate transfer mechanism which transfers the substrate between the functional part and the container mounted on the delivery part.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 12, 2022
    Assignee: Tokyo Electron Limited
    Inventor: Takuya Mori
  • Patent number: 11380621
    Abstract: A semiconductor wafer processing susceptor for holding a wafer having an orientation notch during deposition of a layer on the wafer, having a placement surface for supporting the semiconductor wafer in the rear edge region of the wafer, the placement surface having a stepped outer delimitation, and an indentation of the outer delimitation of the placement surface for placement of the partial region of the edge region of the rear side of the wafer in which the orientation notch is located onto a partial region of the placement surface delimited by the indentation of the outer delimitation of the placement surface. The susceptor is used in a method for depositing a layer on a wafer having an orientation notch, and wafers made of monocrystalline silicon upon which layers are deposited using the susceptor have greater local flatness on both front and rear sides proximate the orientation notch.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 5, 2022
    Assignee: SILTRONIC AG
    Inventors: Reinhard Schauer, Christian Hager
  • Patent number: 11380834
    Abstract: The present disclosure provides a method for making a single photon detector with a modified superconducting nanowire. The method includes: preparing a substrate; modifying a superconducting nanowire with stress on a surface of the substrate; and fabricating a superconducting nanowire single photon detector based on the superconducting nanowire with stress. Based on the above technical solution, in the superconducting nanowire single photon detector provided by the present disclosure, the device material layer film has a certain thickness, the critical temperature of the device material can be reduced, the uniformity of the device material and small superconducting transition width are ensured, thereby improving the detection efficiency of the device.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: July 5, 2022
    Assignee: SHANGHAI INSTITUTE OF MICROSYSTEMS AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: Xin Ou, Lixing You, Qi Jia, Weijun Zhang