Abstract: The present application provides a method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a substrate; forming a first conductive material layer on the substrate; performing plasma treatment on the first conductive material layer to form a first conductive layer; successively forming a second conductive layer, a first block layer, a third conductive layer and a fourth conductive layer on the first conductive layer; forming a dielectric layer on the fourth conductive layer, and forming an ohmic contact layer at a junction of the first conductive layer and the second conductive layer; forming an initial bit line structure; performing NH3/N2 plasma treatment on the initial bit line structure to form a second block layer on a sidewall of the first conductive layer and a third block layer on a sidewall of the ohmic contact layer.

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Abstract: A manufacturing method is provided, which includes processing at least one of a plurality of substrates; stacking the plurality of substrates to manufacture a stacked substrate; and correcting, in the processing, a part of an amount of positional misalignment that is generated among a plurality of substrates in the stacking and correcting, in the stacking, at least a part of the remainder of the amount of positional misalignment.

Abstract: A fingerprint sensor includes: a thin film transistor disposed on a substrate; a first insulating layer disposed on the thin film transistor; a first sensing electrode disposed on the first insulating layer and connected to the thin film transistor; a second insulating layer disposed on the first sensing electrode and including an opening exposing the first sensing electrode; a sensing semiconductor layer disposed in the opening of the second insulating layer and on the first sensing electrode, and including an N-type semiconductor layer, an I-type semiconductor layer, and a P-type semiconductor layer, and a second sensing electrode disposed on the sensing semiconductor layer. An upper surface of the sensing semiconductor layer and an upper surface of the second insulating layer are coplanar.

Abstract: A solid-state imaging device is provided that comprises a first substrate that includes a first multi-layered wiring layer stacked on a first semiconductor substrate, a second substrate that includes a second multi-layered wiring layer and an insulating layer stacked on a second semiconductor substrate, and a third substrate that includes a third multi-layered wiring layer stacked on a third semiconductor substrate. A first coupling structure electrically couples the first and second substrates to each other. A second coupling structure exists on bonding surfaces of the second and third substrates, and includes an electrode junction structure in which electrodes formed on respective bonding surfaces are in direct contact with each other. A first via penetrates the second semiconductor substrate and electrically couples a first electrode to a wiring in the second multi-layered wiring layer. A second via electrically couples the second electrode to another wiring in the third multi-layered wiring layer.

Abstract: An array substrate includes a substrate, the array substrate includes a display region and a detection region. And the detection region includes a thin film transistor located on the substrate and a photodiode located on one side of the thin film transistor away from the substrate, and the array substrate further includes a first inorganic protective layer, an organic protective layer and a second inorganic protective layer located between the thin film transistor and the photodiode. And the first inorganic protective layer, the organic protective layer and the second inorganic protective layer are stacked in sequence in a direction away from the substrate, and an orthographic projection of the photodiode on the substrate is within the range of the orthographic projection of the organic protective layer on the substrate.

Abstract: A method includes moving a wafer transport device to a position above a load port; lowering a hoist unit of the wafer transport device above the load port, wherein the wafer transport device has a plurality of belts, each of the belts is connected to the hoist unit and wound around a respective belt winding drum; detecting sound waves from the belts by using at least one acoustic sensor to measure tensions of the belts; and comparing the tensions from the belts to determine an inclination of the hoist unit.

Abstract: Exemplary methods of semiconductor processing may include coupling a fluid conduit within a substrate support in a semiconductor processing chamber to a system foreline. The coupling may vacuum chuck a substrate with the substrate support. The methods may include flowing a gas into the fluid conduit. The methods may include maintaining a pressure between the substrate and the substrate support at a pressure higher than the pressure at the system foreline.

Abstract: A method includes forming a gate stack over a substrate and a gate spacer on a sidewall of the gate stack; forming a source/drain region in the substrate and adjacent to the gate spacer; forming a first interlayer dielectric layer over the source/drain region; forming a protective layer over the gate stack and in contact with a top surface of the gate spacer; removing the first interlayer dielectric layer after forming the protective layer; forming an etch stop layer over the protective layer; forming a second interlayer dielectric layer over the etch stop layer; etching the second interlayer dielectric layer and the etch stop layer to form an opening that exposes a top surface of the protective layer; and forming a contact plug in the opening.

Abstract: A high electron mobility transistor includes a substrate. A first III-V compound layer is disposed on the substrate. A second III-V compound layer is embedded within the first III-V compound layer. A P-type gallium nitride gate is embedded within the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate. A source electrode is disposed at one side of the gate electrode. A drain electrode is disposed at another side of the gate electrode.

Abstract: The present disclosure provides a semiconductor stack, a semiconductor device and a method for manufacturing the same. The semiconductor device includes a first semiconductor layer and a light-emitting structure. The first semiconductor layer includes a first III-V semiconductor material, a first dopant, and a second dopant. The light-emitting structure is on the first semiconductor layer and includes an active structure. In the first semiconductor layer, a concentration of the second dopant is higher than a concentration of the first dopant. The first dopant is carbon, and the second dopant is hydrogen.

Abstract: A method for providing a piezoelectric device is described. The method includes providing a first electrode layer on a substrate and coating at least one layer of piezoelectric material. The coating using at least one of slot-die coating, dip coating, aerosol coating and R2R coating such that a layer of the at least one layer of piezoelectric material has a variation in thickness of not more than ten percent. The layer(s) of piezoelectric materials are also heat treated. Multiple layers of piezoelectric material may be slot-die coated and heat treated to provide a multilayer having the desired thickness. A second electrode layer is provided on the layer(s) of piezoelectric material.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a first dielectric layer formed over the substrate. The semiconductor device structure also includes a first movable membrane formed over the first dielectric layer. In addition, the first movable membrane has a first corrugated portion and a first edge portion connecting to the first corrugated portion. The semiconductor device structure further includes a second dielectric layer formed over the first movable membrane. In addition, the first edge portion is sandwiched between the first dielectric layer and the second dielectric layer, the first corrugated portion is partially sandwiched between the first dielectric layer and the second dielectric layer and is partially exposed by a cavity, and a bottom surface of the first corrugated portion is lower than a bottom surface of the first edge portion.

Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.

Abstract: A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming active pillars arranged in an array on the substrate, a projection shape of a longitudinal section of each of the active pillars includes a cross shape; forming a first oxide layer on the substrate, where a filling region is formed between adjacent active pillars in the same row; sequentially forming a word line and a dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the active pillars; and forming a capacitor structure on the contact layer.

Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.

Abstract: A superconducting quantum mechanical device includes first, second, third and fourth Josephson junctions connected in a bridge circuit having first, second and third resonance eigenmodes. The device also includes first and second capacitor pads. The first and second capacitor pads and the bridge circuit form a superconducting qubit having a resonance frequency corresponding to the first resonance eigenmode. The device further includes first and second resonator sections. The first and second resonator sections and the bridge circuit form a resonator having a resonance frequency corresponding to the second resonance eigenmode. The device also includes a source of magnetic flux arranged proximate the bridge circuit. The source of magnetic flux is configured to provide, during operation, a magnetic flux through the bridge circuit to cause coupling between the first, second and third resonance eigenmodes when the third resonance eigenmode is excited.

Abstract: In a film-forming technology using charged particles, a disturbance in film thickness distribution caused by leakage magnetic field is suppressed. A film-forming method embodies a technological idea of switching generation and stop of a magnetic field during a film-forming operation so as to stop the generation of the magnetic field during a period when plasma is generated and generate the magnetic field during a period when plasma is not generated.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate with a groove structure formed therein is provided; a laminated structure is formed on the substrate, which includes a first conductive material layer, a second conductive material layer and an insulating material layer from bottom up, and the first conductive material layer fills the groove structure and covers the surface of the substrate; the insulating material layer, the second conductive material layer and the first conductive material layer are sequentially etched to form a bit line structure, in which a process of etching the first conductive material layer includes a first etching stage and a second etching stage, such that a bottom width of the first pattern structure located in the groove structure is not smaller than that of the first pattern structure located outside the groove structure.