Abstract: The present disclosure relates to a semiconductor device, a manufacturing method, an imaging element, and an electronic device capable of reducing manufacturing steps in a stacked structure obtained by stacking two or more semiconductor substrates. The semiconductor device has a stacked structure obtained by stacking at least a first semiconductor substrate in which a first wiring layer is stacked on a first semiconductor layer and a second semiconductor substrate in which a second wiring layer is stacked on a second semiconductor layer. Then, a through via which electrically connects the first semiconductor substrate and the second semiconductor substrate to each other and penetrates at least the first semiconductor layer is formed in an embedded oxide film formed when element isolation of a semiconductor element formed in the first semiconductor layer is performed. The present technology is applicable to, for example, a stacked semiconductor device.

Abstract: An apparatus includes a dielectric tile array including a plurality of dielectric tiles; and a plurality of electroactive (EA) material blocks configured to expand or contract in response to being actuated by the application of an actuation voltage.

Abstract: A method and structure for a transfer process for an acoustic resonator device. In an example, a bulk acoustic wave resonator (BAWR) with an air reflection cavity is formed. A piezoelectric thin film is grown on a crystalline substrate. A first patterned electrode is deposited on the surface of the piezoelectric film. An etched sacrificial layer is deposited over the first electrode and a planarized support layer is deposited over the sacrificial layer, which is then bonded to a substrate wafer. The crystalline substrate is removed and a second patterned electrode is deposited over a second surface of the film. The sacrificial layer is etched to release the air reflection cavity. Also, a cavity can instead be etched into the support layer prior to bonding with the substrate wafer. Alternatively, a reflector structure can be deposited on the first electrode, replacing the cavity.

Abstract: A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip.

Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a non-volatile memory (NVM) transistor including a charge-trapping layer and a blocking dielectric, a field-effect transistor (FET) of a first type including a first gate dielectric having a first thickness, a FET of a second type including a second gate dielectric having a second thickness, and a FET of a third type including a third gate dielectric having a third thickness. In some embodiments, the first, second, and third gate dielectric includes a high dielectric constant (high-K) dielectric layer, and the first thickness is greater than the second thickness, the second thickness is greater than the third thickness. Other embodiments are also described.

Abstract: There is provided a method of processing a wafer having devices formed in respective areas on a face side thereof that are demarcated by a plurality of crossing projected dicing lines on the face side. The method of processing a wafer includes a wafer unit forming step of forming a wafer unit having a wafer, a tape, and an annular frame, a dividing step of dividing the wafer along the projected dicing lines into a plurality of device chips, a pick-up step of picking up one at a time of the device chips from the wafer unit, and a measuring step of measuring the device chip picked up in the pick-up step. The method also includes a distinguishing step, before the pick-up step, of inspecting properties of the devices to distinguish acceptable devices and defective devices among the devices and storing distinguished results.

Abstract: The present disclosure is a photoelectric conversion element including: a photoelectric conversion layer 5 including a first quantum dot 4a and a second quantum dot 4b, a ratio X of the number of heavy metal atoms to the number of oxygen group atoms is less than 2 on a surface of the nanoparticle of the first quantum dot 4a, the ratio X is greater than or equal to 2 on a surface of the nanoparticle of the second quantum dot 4b, and Equation (1) is satisfied: 0.3<N??(1), where N denotes a ratio of the number of second quantum dots to the number of first quantum dots.

Abstract: Provided is a method of evaluating a silicon wafer manufacturing process for mass-producing multiple silicon wafers. Lifetime measurement to silicon wafers mass-produced in the silicon wafer manufacturing process is performed in different locations within a surface of each of the silicon wafers and multiple measurement values are obtained. The representative value is determined for each of the silicon wafers from the multiple measurement values. The determination threshold is obtained for each wafer group including multiple silicon wafers using the representative value for each of the silicon wafers included in the wafer group. Whether the wafer group includes a silicon wafer having a lifetime outlier determined on the basis of the determination threshold among the multiple measurement values obtained for each of the silicon wafers is determined, and whether the manufacturing process may cause a defective product to be produced is determined.

Abstract: A method of processing a workpiece with a disk-shaped blade containing abrasive grains includes the steps of placing an auxiliary plate made of a material having a modulus of elasticity higher than a material of which a front surface side of the workpiece is made, on the front surface side of the workpiece, causing the blade rotated to cut into the front surface side of the workpiece to cut the workpiece as well as the auxiliary plate, and removing the auxiliary plate from the workpiece that has been cut by the blade.

Abstract: A transistor module assembly includes a longitudinally extending load bus bar, a longitudinally extending feed bus bar parallel to the load bus bar, and at least one transistor package operatively connected to the load and feed bus bars. The transistor package includes a drain surface and a source lead. The drain surface is operatively connected to the feed bus bar for receiving current therefrom. The source lead is operatively connected to the load bus bar for dissipating current from the transistor package to the load bus bar.

Abstract: A storage system includes shelves each with a nozzle to supply clean gas into containers, flow amount controllers to control a supply amount of clean gas to a nozzle, a transport apparatus to transfer the containers to and from the shelves, and a controller to control the transport apparatus and the flow amount controllers. The controller makes an assignment of at least one shelf in preparation to store an incoming container and before the occurrence of the incoming container, and controls a flow amount controlling device to supply clean gas to the nozzle in the at least one shelf, based upon the assignment.

Abstract: Devices and methods that can facilitate vertical dispersive readout of qubits of a lattice surface code architecture are provided. According to an embodiment, a device can comprise a first substrate that can have a first side and a second side that can be opposite the first side. The first substrate can comprise a read pad that can be located on the first side and a readout resonator that can be located on the second side. The device can further comprise a second substrate that can be connected to the first substrate. The second substrate can comprise a qubit. In some embodiments, the device can further comprise a recess that can be located on the first side of the first substrate. The recess can comprise the read pad.

Abstract: A multi-voltage domain device includes a semiconductor layer including a first voltage domain, a second voltage domain, and an isolation region that electrically isolates the first voltage domain and the second voltage domain in a lateral direction. The isolation region includes at least one deep trench isolation barrier. A layer stack is arranged on the semiconductor layer and includes a stack insulator layer, a first coil arranged in the stack insulator layer, and a second coil arranged in the stack insulator layer and laterally separated from the first coil in the lateral direction. The first and second coils are magnetically coupled to each other in the lateral direction. The first coil includes terminals arranged vertically over the first region and are electrically coupled to the first voltage domain, and the second coil includes terminals arranged vertically over the second region and are electrically coupled to the second voltage domain.

Abstract: In a piezoelectric device, electrode layers are spaced apart from each other in the direction of the normal thereto. A first piezoelectric layer is interposed between two electrode layers of electrode layers in the direction of the normal. A second piezoelectric layer is provided on an opposite side of the first piezoelectric layer from a base portion. The second piezoelectric layer is interposed between two electrode layers of the electrode layers in the direction of the normal. The half-width of a rocking curve measured by X-ray diffraction for a lattice plane of the first piezoelectric layer substantially parallel to a first main surface is smaller than a half-width for the second piezoelectric layer. The piezoelectric constant of a material defining the first piezoelectric layer is smaller than the piezoelectric constant of a material defining the second piezoelectric layer.

Abstract: Examples include a device including a nanovoided polymer element having a first surface and a second surface, a first plurality of electrodes disposed on the first surface, a second plurality of electrodes disposed on the second surface, and a control circuit configured to apply an electrical potential between one or more of the first plurality of electrodes and one or more of the second plurality of electrodes to induce a physical deformation of the nanovoided polymer element.

Abstract: A method of processing a semiconductor wafer is provided. The method includes installing upper lid. The installation of the upper lid includes placing an inlet manifold on a water box; inserting a jig into a lower gas channel in the water box and inserting into an upper gas channel in the inlet manifold; fastening the water box to the inlet manifold; and removing the jig after the water box engaging with the inlet manifold. The method also includes connecting a shower head on a lower side of the water box; and connecting the upper lid to a housing. The method further includes placing a semiconductor wafer into the housing. In addition, the method includes supplying a process gas over the semiconductor wafer through the upper gas channel, the lower gas channel and the shower head.

Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.

Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located

Abstract: A method of fabricating a neuromorphic device includes forming a variable-resistance layer between a first terminal and a second terminal, the variable-resistance layer varies in resistance based on an oxygen concentration in the variable-resistance layer. The method further includes forming an electrolyte layer over the variable-resistance layer that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage. The method further includes forming a gate layer over the electrolyte layer to apply a voltage on the electrolyte layer and the variable-resistance layer, the gate layer formed using an oxygen scavenging material.