Patents Examined by Jarrett J. Stark
  • Patent number: 11805644
    Abstract: Provided is a manufacturing method of a memory device, including: forming a stacked layer on a substrate; patterning the stacked layer to form a plurality of openings in the stacked layer; forming a spacer on a sidewall of the openings; performing a first etching process by using the spacer as a mask to form a plurality of stack structures, wherein the spacer is embedded in the stack structures, such that a width of an upper portion of the stack structures is less than a width of a lower portion thereof; forming a dielectric layer on the stack structures and the spacer; and respectively forming a plurality of contact plugs on the substrate between the stack structures.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: October 31, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Jian-Ting Chen, Yao-Ting Tsai, Hsiu-Han Liao
  • Patent number: 11800729
    Abstract: An imaging element 10 includes a first electrode 21, a charge accumulation electrode 24 disposed apart from the first electrode 21, a photoelectric conversion unit 23 formed in contact with the first electrode 21 and above the charge accumulation electrode 24 with an insulation layer 82 interposed between the photoelectric conversion unit 23 and the charge accumulation electrode 24, and a second electrode 22 formed on the photoelectric conversion unit 23. The photoelectric conversion unit 23 includes a photoelectric conversion layer 23A and an inorganic oxide semiconductor material layer 23B disposed in an order of the photoelectric conversion layer 23A and the inorganic oxide semiconductor material layer 23B from the second electrode side. The inorganic oxide semiconductor material layer 23B contains indium (In) atoms, tin (Sn) atoms, titanium (Ti) atoms, and zinc (Zn) atoms.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: October 24, 2023
    Assignee: SONY CORPORATION
    Inventor: Toshiki Moriwaki
  • Patent number: 11788708
    Abstract: A lens includes a cover part and a light-shielding part. The cover part includes a lens part, a connection part, and a flange part which are formed of a thermosetting first resin and continuous to one another. The light-shielding part covers an outer lateral side of the connection part and is formed of a second resin having a greater light-absorptance or a greater light-reflectance than the first resin.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: October 17, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Tsuyoshi Okahisa, Toshiyuki Fujii
  • Patent number: 11791788
    Abstract: The present disclosure relates to parametric amplifiers that can be used in the presence of a magnetic field. In particular the present disclosure relates to an integrated signal amplifier that comprises: a quantum dot; a first conductive electrode arranged in a manner such that tunnelling of electrons to the quantum dot is prevented; and a second conductive electrode arranged in a manner such tunnelling of electrons to the quantum dot is permitted. When an oscillating signal is applied across the first and second electrodes, the equivalent capacitance across the first and the second electrodes oscillates at the frequency of the oscillating signal.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: October 17, 2023
    Assignee: NEWSOUTH INNOVATIONS PTY LTD
    Inventor: Matthew G. House
  • Patent number: 11791331
    Abstract: Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: October 17, 2023
    Assignee: Intel Corporation
    Inventors: Nicholas A. Thomson, Kalyan C. Kolluru, Adam Clay Faust, Frank Patrick O'Mahony, Ayan Kar, Rui Ma
  • Patent number: 11769690
    Abstract: A device includes a substrate, a first metal feature over the substrate, first and second spacers, a first dielectric layer, and a second metal feature. The first and second spacers are on opposite sidewalls of the conductive feature, respectively. The first dielectric layer is in contact with the first spacer, in which a top surface of the protection layer is higher than a top surface of the first spacer. The second metal feature is electrically connected to the first metal structure and in contact with a top surface and a sidewall of the protection layer.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Chia-Hao Chang, Wai-Yi Lien, Yu-Ming Lin
  • Patent number: 11766756
    Abstract: A substrate support apparatus 100 has a support part 10 for supporting a substrate W; a moving part 50 which is adapted to abut on the support part 10 and to move the support part 10 along an axis direction; a fluid pipe 60 at least a part of which is provided in the moving part 50, through which fluid flows and an outlet port 61 of which is covered by the support part 10 when the moving part 50 abuts on the support part 10; and a detection part 90 which detects a state of the fluid.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: September 26, 2023
    Assignee: EBARA CORPORATION
    Inventor: Mitsuru Miyazaki
  • Patent number: 11756817
    Abstract: The inventive concept provides an apparatus and method for processing a substrate. The apparatus includes an index module and a processing module that is disposed adjacent to the index module and that processes the substrate. The index module includes one or more load ports, on each of which a carrier having the substrate received therein is placed, a side storage that stores the substrate subjected to a process in the processing module and removes fumes on the substrate, and a transfer frame including an index robot that transfers the substrate between the carrier placed on the load port, the side storage, and the processing module. The side storage includes a housing having an interior space, a partitioning unit that partitions the interior space into a plurality of receiving spaces independent of one another, and an exhaust unit that independently and separately evacuates the plurality of receiving spaces.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 12, 2023
    Assignee: SEMES CO., LTD.
    Inventors: Dukhyun Son, Sunghwan Hong
  • Patent number: 11757055
    Abstract: An electromagnetic wave detector 100 comprises: a substrate 5 having a front surface and a back surface; an insulating layer 4 formed of a rare earth oxide, which is provided on the front surface of the substrate 5; a pair of electrodes 2 provided on the insulating layer 4 so as to be arranged to face each other across a gap; and a two-dimensional material layer 1 provided on the insulating layer 4 so as to be electrically connected to the pair of electrodes 2. The rare earth oxide contains a base material made of an oxide of a first rare earth element, and a second rare earth element different from the first rare earth element, which is activated in the base material.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: September 12, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shoichiro Fukushima, Masaaki Shimatani, Shimpei Ogawa
  • Patent number: 11749545
    Abstract: A substrate-floatation-type laser processing apparatus and a method for measuring a floating height, capable of improving performance of laser processing are provided. A substrate-floatation-type laser processing apparatus according to an embodiment includes a stage configured to float and convey a substrate, and a floating-height measurement apparatus configured to measure a floating height H of the substrate. Note that a distance between the floating-height measurement apparatus and the substrate can be automatically adjusted according to the measured floating height H. The floating height H of the substrate is measured by applying laser light to the substrate and the stage. The distance between the floating-height measurement apparatus and the substrate is adjusted by using a feedback mechanism in which the measured floating height of the substrate is used as an input.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: September 5, 2023
    Assignee: JSW AKTINA SYSTEM CO., LTD
    Inventors: Daisuke Hayashi, Takahiro Mikami, Yuki Suzuki
  • Patent number: 11751418
    Abstract: A display panel may include a first display substrate, a second display substrate disposed over the first display substrate, and a sealing member bonding the first display substrate and the second display substrate. The sealing member may include a frit sealing member including an outer region and an inner region, with the inner region disposed next to an inner side of the outer region and having a first crystallization temperature lower than a second crystallization temperature of the outer region, and an organic sealing member disposed next to an inner side of the frit sealing member.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: September 5, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Kim, Junehyoung Park
  • Patent number: 11744132
    Abstract: A flexible display device includes a protection member, a first adhesion member, a display member, a second adhesion member, and a window member. A thickness of the display member is less than a sum of thicknesses of the protection member and the window member. The display member includes a display panel layer, a touch sensing layer, and a reflection prevention layer integrated with each other to reduce a thickness of the flexible display device. The reduction in thickness enables the flexible display device to be bent with a relatively small radius of curvature, as well as to be repeatedly bent (or otherwise flexed) with reduced potential for delamination of the first and second adhesion members.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: August 29, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Taehoon Yang, Yongsu Lee, Sungchul Kim, Sunghoon Kim, Sungsik Yun, Kyoungah Lee
  • Patent number: 11735481
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: 11735457
    Abstract: To improve uniformity in polishing of a polished surface of a substrate regardless of a tolerance of a diameter of the substrate. A substrate processing apparatus includes a table 100, a pad holder 226, a swing mechanism, a supporting member 300A, 300B, a measuring instrument 400, and a driving mechanism 320. The table 100 supports a substrate WF. The pad holder 226 holds a polishing pad 222. The polishing pad 222 polishes the substrate WF supported to the table 100. The swing mechanism swings the pad holder 226. The supporting member 300A, 300B supports the polishing pad 222 swung to outside the table 100 by the swing mechanism. The measuring instrument 400 is configured to measure a diameter of the substrate WF. The driving mechanism 320 adjusts a position of the supporting member 300A, 300B with respect to the substrate WF supported to the table 100 according to the diameter of the substrate WF measured by the measuring instrument 400.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 22, 2023
    Assignee: Ebara Corporation
    Inventors: Nobuyuki Takada, Hozumi Yasuda
  • Patent number: 11721774
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region comprising a dopant having a first doping type. A deep well region is disposed within the semiconductor substrate, where the deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a second dopant having a second doping type opposite the first doping type, where the second dopant comprises gallium.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Yun Yang, Chun-Yuan Chen, Ching I Li
  • Patent number: 11711917
    Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: July 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
  • Patent number: 11703229
    Abstract: A temperature adjustment apparatus for a high temperature oven, comprising: an oven comprising an oven cavity, at least one intake manifold, at least one exhaust manifold, an inner casing cover, at least one heating element, and a chamber door; wherein a processing chamber is formed inside the oven cavity; the inner casing cover is disposed around an inner wall of the oven cavity; the inner casing cover is heated by at least one of the heating elements, and the processing chamber is heated by the inner casing cover in the form of thermal radiation; and a gas reprocessing device comprising a gas recovery device, wherein a gas in the processing chamber is sucked into the gas reprocessing device by using the gas recovery device, and the sucked gas can be directly discharged from the gas reprocessing device or reprocessed and flows back to the processing chamber.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: July 18, 2023
    Inventor: Yi-Ming Hung
  • Patent number: 11706988
    Abstract: A piezoelectric device includes a piezoelectric single crystal body with a homogeneous polarization state and of which at least a portion flexurally vibrates, an upper electrode on an upper surface of the piezoelectric single crystal body, a lower electrode on a lower surface of the piezoelectric single crystal body, and a supporting substrate below the piezoelectric single crystal body. A recess extends from a lower surface of the supporting substrate toward the lower surface of the piezoelectric single crystal body.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: July 18, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shinsuke Ikeuchi, Tetsuya Kimura, Katsumi Fujimoto, Yutaka Kishimoto, Fumiya Kurokawa
  • Patent number: 11694890
    Abstract: A substrate processing method for forming a nitride film on a substrate, includes: a raw material gas supply step of supplying a raw material gas containing an element to be nitrided; a hydrogen gas supply step of, after the raw material gas supply step, supplying a hydrogen gas activated by plasma; a thermal nitriding step of supplying a first nitriding gas containing nitrogen activated by heat and nitriding the element; and a plasma nitriding step of supplying a second nitriding gas containing nitrogen activated by plasma and nitriding the element.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: July 4, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kiwamu Ito, Keiko Hosoe, Yamato Tonegawa
  • Patent number: 11694997
    Abstract: In some embodiments, the present disclosure relates to method of forming an integrated circuit, including forming a semiconductor device on a frontside of a semiconductor substrate; depositing a dielectric layer over a backside of the semiconductor substrate; patterning the dielectric layer to form a first opening in the dielectric layer so that the first opening exposes a surface of the backside of the semiconductor substrate; depositing a glue layer having a first thickness over the first opening; filling the first opening with a first material to form a backside contact that is separated from the semiconductor substrate by the glue layer; and depositing more dielectric layers, bonding contacts, and bonding wire layers over the dielectric layer to form a second bonding structure on the backside of the semiconductor substrate, so that the backside contact is coupled to the bonding contacts and the bonding wire layers.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: July 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Tzu Chen, Hsing-Chih Lin, Min-Feng Kao