Abstract: A semiconductor wafer transport apparatus having a transport arm and at least one end effector. An optical edge detection sensor is coupled to the transport arm and is configured so as to register and effect edge detection of a wafer supported by the end effector. An illumination source illuminates a surface of the wafer and is disposed with respect to the optical edge detection sensor so that the surface directs reflected surface illumination, from the illumination source, toward the optical edge detection sensor, and optically blanks, at the peripheral edge of the wafer, background reflection light of a background, viewed by the optical edge detection sensor coincident with linear traverse of the wafer supported by the at least one end effector. The peripheral edge of the wafer is defined in relief in image contrast to effect edge detection coincident with traverse of the wafer supported by the end effector.

Abstract: Disclosed are various embodiments for a piezo-composite transducer that is flexible such that it may conform to regular or irregular shapes. A flexible piezo-composite transducer may include an active piezoelectric material, such as PZT-5H, and a passive polymer matrix formed of a flexible material, such as polydimethylsiloxane (PDMS). The flexible piezo-composite transducer may include a first side and a second side, where each of the first side and the second side include a first electrode and a second electrode deposited thereon, respectively. At least one of the first electrode and the second electrode may include a silver nanowire (AgNW) and PDMS electrode that is flexible.

Abstract: An electrostatic chuck is configured to adsorb and retain an object thereon. The electrostatic chuck includes: a base body on which the object is mounted; an electrostatic electrode that is provided in the base body; a plurality of heating elements that are provided in the base body; a plurality of current control elements that are provided in the base body, and each of which is connected in series with a corresponding one of the heating elements; and a control circuit that is provided in the base body, and that is connected to the current control elements and configured to control operations of the current control elements.

Abstract: Examples of a semiconductor device includes a transistor region formed in a semiconductor substrate having a first conductivity type drift layer, and a diode region formed to be adjacent to the transistor region in the semiconductor substrate, wherein the diode region has a second conductivity type anode layer formed on the drift layer and a first conductivity type cathode layer formed on the lower side of the drift layer, and the cathode layer has an adjacent region contacting the transistor region, the adjacent region having a depth, from a lower surface of the semiconductor substrate, which becomes shallower toward the transistor region and having first conductivity type impurity concentration which decreases toward the transistor region.

Abstract: An optoelectronic device is disclosed, comprising: a photodiode array including a plurality of first photodiodes, each first photodiode including a respective n+ region and a respective n-well region; a guide array disposed over the photodiode array, the guide array including a plurality of guide members separated from one another by a layer of light-blocking material, the guide members being aligned with the n+ regions of the first photodiodes, such that each guide member is disposed over a different respective n+ region, and the layer of light-blocking material being aligned with the n-well regions of the first photodiodes; and a filter array disposed over the guide array, the filter array including a plurality of bandpass filters, each bandpass filter being aligned with a different one of the plurality of guide members, each bandpass filter having a different transmission band.

Abstract: Piezoelectrically actuated devices constructed from thin semiconductor membranes bonded directly to piezoelectric substrates are provided. Methods for fabricating these devices are also provided. The bonding of the semiconductor to the piezoelectric material does not require the use of any intermediate layers, such as bonding agents.

Abstract: An apparatus for manufacturing a display device includes: a first housing having a first chamber; a support member disposed in the first chamber and including a frame having a plurality of openings; a plurality of adhesive patterns disposed on the frame; and a plurality of electrostatic supports overlapping the plurality of openings and supported for reciprocal movement in respective ones of the openings.

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.

Abstract: A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer, a first polymer layer, and a first conductive via extending through the first polymer layer. The first polymer layer is in physical contact with the first passivation layer.

Abstract: A method for depositing an object, including: —approaching, in an enclosure, a holder in the direction of a carrier substrate, then—transferring, in the enclosure, the object from the holder to an area for depositing the carrier substrate. The transfer step is preferably carried out when the inside of the enclosure is in a vacuum at a pressure below 10?6 bar.

Abstract: A method for selectively forming a silicon nitride film on a substrate comprising a first metallic surface and a second dielectric surface by a cyclical deposition process is disclosed. The method may comprise contacting the substrate with a first reactant comprising a silicon halide source and contacting the substrate with a second reactant comprising a nitrogen source, wherein the incubation period for the first metallic surface is less than the incubation period for the second dielectric surface. Semiconductor device structures comprising a selective silicon nitride film are also disclosed.

Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.

Abstract: Provided are a three-dimensional flash memory device supporting a bulk erase operation and a method of manufacturing the three-dimensional flash memory device. The three-dimensional flash memory device supporting a bulk erase operation includes: a string including a channel layer extending in one direction and a plurality of electrode layers stacked vertically with respect to the channel layer; an upper wiring layer on the string; at least one intermediate wiring layer arranged between the plurality of electrode layers through the channel layer in an intermediate region of the string; a lower wiring layer under the string; and at least one connector arranged in the at least one intermediate wiring layer and connecting, to each other, at least two channel layers divided by the at least one intermediate wiring layer.

Abstract: The electrostatic chuck device includes: a base having one main surface serving as a mounting surface on which a plate-shaped sample is mounted; and an electrode for electrostatic attraction provided on a side opposite to the mounting surface in the base or in an interior of the base, in which the electrode for electrostatic attraction is made of a composite sintered body that includes a matrix phase having insulation properties and a dispersed phase having a lower volume resistivity value than the matrix phase, in any cross section of the composite sintered body, a region of the dispersed phase, which is surrounded by the matrix phase and is independent, includes aggregated portions having a maximum Feret diameter of 30 ?m or more, and one or more of the aggregated portions are present in a range of 2500 ?m2 in any cross section of the sintered body.

Abstract: Apparatus, methods, and systems are disclosed for robust scalable topological quantum computing. Quantum dots are fabricated as van der Waals heterostructures, supporting localized topological phases and non-Abelian anyons (quasiparticles). Large bandgaps provide noise immunity. Three-dot structures include an intermediate quantum dot between two computational quantum dots. With the intermediate quantum dot in an OFF state, quasiparticles at the computational quantum dots can be isolated, with long lifetimes. Alternatively, the intermediate quantum dot can be controlled to decrease the quasiparticle tunneling barrier, enabling fast computing operations. A computationally universal suite of operations includes quasiparticle initialization, braiding, fusion, and readout of fused quasiparticle states, with, optionally, transport or tunable interactions—all topologically protected. Robust qubits can be operated without error correction.

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Abstract: A quantum battery manufacturing method includes: providing a p-type semiconductor substrate including a first conductive substrate and a p-type semiconductor layer disposed on one surface of the first conductive substrate; providing an n-type semiconductor substrate including a second conductive substrate and an n-type semiconductor layer disposed on one surface of the second conductive substrate; and forming an electricity storage layer between the p-type semiconductor substrate and the n-type semiconductor substrate, and attaching two sides of the electricity storage layer respectively to the p-type semiconductor layer and the n-type semiconductor layer to form a quantum battery. The electricity storage layer is formed by heating a thermoplastic polymer to soften and become a liquid, mixing the liquid with energized core-shell particles, and coating a substrate with the mixture. Core-shell particles are disposed on a conductive substrate and irradiated with ultraviolet rays for energization.

Abstract: A poling apparatus for poling a polymer thin film formed on a workpiece carried by a workpiece carrier. The workpiece has grounding electrodes and grounding pads located at edges, and a thin film covering the grounding electrodes but exposing the grounding pads. The workpiece carrier has carrier electrodes located around the workpiece and inside grounding ports at the bottom. The poling apparatus includes, in a poling chamber, a poling source generating a plasma, a Z-elevator to raise the workpiece carrier toward the poling source using the grounding ports, and grounding mechanisms including downwardly biased electrical contacts which, when the workpiece carrier is raised by the Z-elevator, connect the grounding pads of the workpiece with the carrier electrodes, to ground the workpiece. The poling apparatus additionally includes preparation platform and transfer platform with conveyer systems with rollers and Z-elevators to move the workpiece carrier in and out of the poling chamber.

Abstract: A semiconductor device includes a stacked structure with conductive layers and insulating layers that are stacked alternately with each other, an insulating pillar passing through the stacked structure, a first channel pattern surrounding a sidewall of the insulating pillar, a second channel pattern surrounding the sidewall of the insulating pillar, a first insulator formed between the first channel pattern and the second channel pattern, and a memory layer surrounding the first channel pattern, the second channel pattern, and the first insulator, the memory layer with a first opening located that is between the first channel pattern and the second channel pattern.

Abstract: A system-on-chip may include an inductor-capacitor oscillator monolithically integrated into the system-on-chip The inductor-capacitor oscillator may be configured to improve frequency stability and reduce noise when compared to a resistor-capacitor oscillator. Methods of making integrated oscillators may involve forming an inductor at least partially while forming a BEOL structure on a substrate. A capacitor supported on and/or embedded within the semiconductor material of the substrate may be formed before or while forming the BEOL structure. The inductor may be connected to the capacitor in parallel at least partially utilizing the BEOL structure to form an integrated inductor-capacitor oscillator.