Abstract: A vertical semiconductor device includes a semiconductor body having semiconductor portions of semiconductor elements of the vertical semiconductor device, a front side contact on a front surface of the semiconductor body and a back side contact on an opposite back surface of the semiconductor body, and a trench structure extending from the front surface into the semiconductor body. The trench structure includes an etch stop layer lining an inner surface of the trench structure and surrounding a void within the trench structure.

Abstract: A semiconductor device is disclosed including material for absorbing EMI and/or RFI The device includes a substrate (202), one or more semiconductor die (224,225), and molding compound around the one or more semiconductor die (224,225). The material for absorbing EMI and/or RFI may be provided within or on a solder mask layer (210) on the substrate (202). The device may further include EMI/RFI-absorbing material around the molding compound and in contact with the EMI/RFI-absorbing material on the substrate to completely enclose the one or more semiconductor die in EMI/RFI-absorbing material.

Abstract: In an example, a memory device includes a staircase comprising a flight of stairs and a plurality of pass transistors directly under the staircase. The stairs of the flight of stairs are respectively coupled to different tiers of memory cells, and a different pass transistor of the plurality of pass transistors is coupled to each of the stairs of the flight of stairs.

Abstract: A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.

Abstract: A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

Abstract: A field effect transistor device comprises a semiconductor substrate, a doped source layer arranged on the semiconductor substrate, an insulator layer arranged on the doped source layer, a fin arranged on the insulator layer, a source region extension portion extending from the doped source layer and through the fin, a gate stack arranged over a channel region of the fin and adjacent to the source region extension portion, a drain region arranged on the fin adjacent to the gate stack; the drain region having a graduated doping concentration.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. An example device may include: a fin formed on a substrate; a gate stack formed on the substrate and intersecting the fin, wherein the gate stack is isolated from the substrate by an isolation layer, and a Punch-Through Stopper (PTS) formed under the fin, including a first section directly under a portion of the fin where the fin intersects the gate stack and second sections on opposite sides of the first section, wherein the second sections each have a doping concentration lower than that of the first section.

Abstract: A semiconductor device includes a first well that is disposed in a semiconductor substrate. The semiconductor device further includes a second well that is disposed in the semiconductor substrate. The semiconductor device further includes a source region, a drain region, and a gate structure between the source region and the drain region. The gate structure is disposed above the first well. The source region includes a first conducting contact above the first well and. The drain region includes a second conducting contact above the second well, the drain region being connected with the second well at least partially through a first epi region. The first epi region and the second well are configured to lower a first driving voltage applied on the source region and the drain region to a second voltage applied on the gate structure.

Abstract: The inventive concepts provide magnetic memory devices and methods forming the same. The method includes sequentially forming a first magnetic conductive layer and a capping layer on a substrate, patterning the capping layer and the first magnetic conductive layer to form a first magnetic conductive pattern and a capping pattern, forming an interlayer insulating layer exposing the capping pattern on the substrate, removing the capping pattern to expose the first magnetic conductive pattern, forming a tunnel barrier layer and a second magnetic conductive layer on the first magnetic conductive pattern and the interlayer insulating layer, and patterning the second magnetic conductive layer and the tunnel barrier layer to form a second magnetic conductive pattern and a tunnel barrier pattern.

Abstract: A semiconductor device includes a substrate having an edge, a semiconductor layer provided on a substrate, an electrode pad provided on the semiconductor layer, an inorganic insulating film having a first opening through which an upper surface of the electrode pad is exposed, and a resin film provided on the inorganic insulating film, the resin film having a second opening and a third opening separated from each other, where the upper surface of the electrode pad is exposed through the second opening, where the third opening is located between the second opening and the edge of the substrate, and where a bottom of the third opening is constituted by the resin film or the inorganic insulating film.

Abstract: A structure comprises a p-type substrate, a deep n-type well and a deep p-type well. The deep n-type well is adjacent to the p-type substrate and has a first conductive path to a first terminal. The deep p-type well is in the deep n-type well, is separated from the p-type substrate by the deep n-type well, and has a second conductive path to a second terminal. A first n-type well is over the deep p-type well. A first p-type well is over the deep p-type well.

Abstract: A resin-sealed module is provided which reduces the warpage of a substrate and the detachment between a sealing resin and the substrate which occur during re-reflow, has the excellent flatness of the top and bottom surfaces, and reduces the occurrence of the short failures. A resin layer made of a thermoplastic resin is arranged on top of a substrate, and a resin layer made of a thermosetting resin is arranged on top of this resin layer, thereby reducing the warpage of the substrate and the detachment between the sealing resin and the substrate which occur during re-reflow.

Abstract: The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.

Abstract: A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a first capacitor plate conductor formed with a cylinder-shaped storage node electrode formed in the multi-layer stack, a capacitor dielectric layer surrounding the cylinder-shaped storage node electrode, and a second capacitor plate conductor formed from a conductive layer in the multi-layer stack that is sandwiched between a bottom and top dielectric layer, where the cylinder-shaped storage node electrode is surrounded by and extends through the conductive layer.

Abstract: A FinFET and a method of manufacturing the same are disclosed. The method includes forming a semiconductor fin. The method further includes forming a first region, the first region being one of a source region and a drain region. The method further includes forming a sacrificial spacer. The method further includes forming a second region with the sacrificial spacer as a mask, the second region being the other one of the source region and the drain region. The method further includes removing the sacrificial spacer. The method further includes replacing the sacrificial spacer with a gate stack comprising a gate conductor and a gate dielectric that separates the gate conductor from the semiconductor fin.

Abstract: A semiconductor device may include interlayer insulating layers stacked in a first direction and separated from each other, word lines formed between the interlayer insulating layers, and sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed. The semiconductor device may also include cell contact plugs each including a first pillar portion passing through at least one of the interlayer insulating layers and the sacrificial insulating layers in the first direction, and a first protruding portion protruding from a sidewall of the first pillar portion and contacting a sidewall of one of the word lines, wherein the cell contact plugs have different depths.

Abstract: A manufacturing of a package carrier includes the following steps. Two base metal layers are bonded together. Two supporting layers are laminated onto the base metal layers respectively. Two release metal films are disposed on the supporting layers respectively. Each release metal film includes a first metal film and a second metal film separable from each other. Two first patterned metal layers are formed on the release metal films respectively. Each first patterned metal layer includes a pad pattern. Two dielectric layers are formed on the release metal films respectively and cover the corresponding first patterned metal layers. Each dielectric layer has a conductive via connecting to the corresponding pad pattern. Two second patterned metal layers are formed on the dielectric layers respectively. Each second patterned metal layer at least covers the conductive via. The base metal layers are separated from each other to form two independent package carriers.

Abstract: The present invention pertains to a semiconductor light-receiving element and a method for manufacturing the same, enabling operation in a wide wavelength bandwidth and achieving fast response and high response efficiency. A PIN type photodiode made by sequentially layering on top of the substrate a Si layer of a first conductivity type, a non-doped Ge layer and a Ge layer of a second conductivity type that is the opposite type of the first conductivity type and a Ge current-blocking mechanism is provided in at least part of the periphery of the PIN type photodiode.

Abstract: Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.

Abstract: A semiconductor device that improves noise performance includes a circuit substrate, an enclosing case, and a metal part. A control circuit is mounted on the front surface of the circuit substrate. The enclosing case is a resin case in which semiconductor elements are installed. The metal part, included inside the enclosing case, includes a first mounting portion, a second mounting portion, and a bus bar. The first mounting portion mounts the circuit substrate on the enclosing case, and is connected to a ground pattern of the circuit substrate when mounting. The second mounting portion mounts an external instrument on the enclosing case, and is grounded when mounting. The bus bar connects the first mounting portion and second mounting portion.