Abstract: An avalanche photodiode includes a GeOI substrate; an I—Ge absorption layer configured to absorb an optical signal and generate a photo-generated carrier; a first p-type SiGe layer, a second p-type SiGe layer, a first SiGe layer, and a second SiGe layer, where a Si content in any one of the SiGe layers is less than or equal to 20%; a first SiO2 oxidation layer and a second SiO2 oxidation layer; a first taper type silicon Si waveguide layer and a second taper type silicon Si waveguide layer; a heavily-doped n-type silicon Si multiplication layer; and anode electrodes and a cathode electrode.

Abstract: A light emitting device package, comprises a light emitting structure having first and second electrodes insulated from each other; and a support structure. The support structure comprises: a first support electrode electrically connected to the first electrode of the light emitting structure; a second support electrode electrically connected to the second electrode of the light emitting structure, the second support electrode spaced apart from, and electrically insulated from, the first support electrode; and a support connection portion between the first support electrode and the second support electrode. The light emitting structure includes a protrusion portion that protrudes in a horizontal direction beyond a sidewall of at least one of the first support electrode and the second support electrode so that a void is present below the protrusion portion and above a plane extending from bottoms of the first and second support electrodes.

Abstract: A lighting emitting diode including: an n side layer and a p side layer formed by nitride semiconductors respectively; an active layer comprising a nitride semiconductor is between the n side layer and the p side layer; wherein, the n-side layer is successively laminated by an extrinsically-doped buffer layer and a compound multi-current spreading layer; the compound multi-current spreading layer is successively-laminated by a first current spreading layer, a second current spreading layer and a third current spreading layer; the first current spreading layer and the third current spreading layer are alternatively-laminated layers comprising a u-type nitride semiconductor layer and an n-type nitride semiconductor layer; the second current spreading layer is a distributed insulation layer formed on the n-type nitride semiconductor layer; and the first current spreading layer is adjacent to the extrinsically-doped buffer layer; and the third current spreading layer is adjacent to the active layer.

Abstract: A metrology system for determining overlay is disclosed. The system includes an optical assembly for capturing images of an overlay mark and a computer for analyzing the captured images to determine whether there is an overlay error. The mark comprises first and second regions that each include at least two separately generated working zones, juxtaposed relative to one another, configured to provide overlay information in a first direction, and include a periodic structure having coarsely segmented elements. The mark comprises third and fourth regions that each include at least two separately generated working zones, juxtaposed relative to one another, configured to provide overlay information in a second direction, and include a periodic structure having coarsely segmented elements.

Abstract: Methods of forming and resulting devices are described that include graphene devices on boron nitride. Selected methods of forming and resulting devices include graphene field effect transistors (GFETs) including boron nitride.

Abstract: A field effect transistor that has a source, a drain, a gate, a semiconductor region, and a dielectric region. The dielectric region is located between the semiconductor region and the gate. Negatively charged ions are located within the dielectric layer underneath the gate.

Abstract: A variable capacitance device that includes a semiconductor substrate, a redistribution layer disposed on a surface of the semiconductor substrate, and a plurality of terminal electrodes including first and second input/output terminals, a ground terminal and a control voltage application terminal. Moreover, a variable capacitance element section is formed in the redistribution layer from a pair of capacitor electrodes connected to the first and second input/output terminals, respectively, and a ferroelectric thin film disposed between the capacitor electrodes. Further, an ESD protection element is connected between the one of the input/output terminals and the ground terminal is formed on the surface of the semiconductor substrate.

Abstract: A method of increasing a work function of an electrode is provided. The method comprises obtaining an electronegative species from a precursor using electromagnetic radiation and reacting a surface of the electrode with the electronegative species. An electrode comprising a functionalized substrate is also provided.

Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

Abstract: A substrate incorporating semiconductor regions electrically isolated by shallow trenches filled with hexagonal, textured or columnar boron nitride. A process for filling shallow trenches in a semiconductor substrate with columnar textured boron nitride using pulsed plasma enhanced chemical vapor deposition (Pulsed PECVD) and plasma assisted atomic layer deposition (PAALD).

Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

Abstract: A semiconductor device in which the electrical connection is established using conductive pins and a printed wiring board, wherein the printed wiring board is mounted parallel to an insulated circuit board to prevent poor bonding of the conductive pins. A third-type conductive pin is arranged in such a manner as to be connected to a first metal layer at a position farther than a first-type conductive pin arranged at a position farthest from a side that is in contact with a gap between island regions. Similarly, another third-type conductive pin is arranged in such a manner as to be connected to another first metal layer at a position farther than another first-type conductive pin arranged at a position farthest from another side that is in contact with the gap between the island regions.

Abstract: Disclosed is an organic light emitting display device that comprises a first light emitting unit between a first electrode and a second electrode, the first light emitting unit including a first hole transporting layer and a first light emitting layer; and a second light emitting unit between the first light emitting unit and the second electrode, the second light emitting unit including a second hole transporting layer and a second light emitting layer that emits a light of the same color as a light emitted by the first light emitting layer. An increase in driving voltage caused by a shift of an emission zone in the first light emitting layer or the second light emitting layer by prolonged driving is minimized which solves a problem of increased power consumption and improves the lifetime of the organic light emitting display device.

Abstract: A method for manufacturing a phase-change device may include the following steps: preparing a substrate; preparing a first dielectric layer, which may be positioned on the substrate; preparing a first electrode, which may be positioned in the first dielectric layer; forming a phase-change material layer, which may overlap the first electrode; processing (e.g., etching) the phase-change material layer to form a phase-change member, which may be electrically connected to the first electrode; forming an etch-stop layer, which may overlap and/or cover the phase-change member; forming an intermediary layer, which may be positioned on the etch-stop layer; forming a second dielectric layer, which may be positioned on the intermediary layer; and forming a second electrode, which may extend through the second dielectric layer, the intermediary layer, and the etch-stop layer and may be electrically connected to the phase-change member.

Abstract: A semiconductor device includes a first conductivity type semiconductor layer that includes a wide bandgap semiconductor and a surface. A trench, including a side wall and a bottom wall, is formed in the semiconductor layer surface, and a Schottky electrode is connected to the surface. Opposite edge portions of the bottom wall of the trench each include a radius of curvature, R, satisfying the expression 0.01 L<R<10 L, where L represents the straight-line distance in a width direction of the trench between the opposite edge portions.

Abstract: A vertical transistor includes a source layer arranged on a substrate; a channel extending vertically from the source layer; a drain arranged on a distal end of the channel that opposes the source layer, the drain including an epitaxial growth; and a drain contact wrapped around exposed areas of the drain and filling a cavity having a liner layer disposed sidewalls of the drain contact.

Abstract: The present invention relates to a display device, comprising: a substrate comprising a display region and a non-display region surrounding the display region; a first conductive layer disposed on the substrate; a semiconductor layer disposed on the substrate and partially covering the first conductive layer; and a second conductive layer disposed on a top surface of the semiconductor layer; and there is a spacing between a first side of the semiconductor layer and a second side of the second conductive layer from a top view, wherein the first side of the semiconductor layer is adjacent to the second side of the second conductive layer; wherein the spacing in the display region is a first distance, the spacing in the non-display region is a second distance, and the first distance is smaller than the second distance.

Abstract: The present disclosure is directed to LED components, methods and systems using such components, having light emitter devices with emissions tuned to meet CRI and LER goal values at a defined CCT. These emitter devices and methods may use a combination of light emitting diodes and quantum dots to tune the emission to meet these criteria. The quantum dots may incorporate additional features to protect the quantum dots from environmental conditions and improve heat dissipation, such as coatings and thermally conductive features.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate, the substrate having a first source/drain feature and a second source/drain feature formed thereon. The semiconductor device further includes a first nanowire on the first source/drain feature and a second nanowire on the second source/drain feature, the first nanowire extending vertically from an upper surface of the first source/drain feature and the second nanowire extending vertically from an upper surface of the second source/drain feature. The semiconductor device further includes a third nanowire extending from an upper end of the first nanowire to an upper end of the second nanowire, wherein the first nanowire, the second nanowire and the third nanowire form a channel.

Abstract: A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.