Patents Examined by Jasmine J B Clark
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Patent number: 6744129Abstract: A ground shield for an integrated component device to prevent coupling between integrated capacitors and/or inductors and other integrated components. Components are formed upon a substrate. A conductive metal layer is formed or deposited thereon. The conductive metal layer is electrically connected to ground and an isolation layer is formed or deposited upon the conductive metal layer. An integrated capacitor, for example a MIM-type capacitor, is then formed upon the isolation layer. The grounded conductive metal layer absorbs electrical noise such that coupling between the capacitor and other components is prevented.Type: GrantFiled: January 11, 2002Date of Patent: June 1, 2004Assignee: Microtune (San Diego), Inc.Inventors: Lee Chew, Jonathon Y. Cheah
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Patent number: 6740536Abstract: Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.Type: GrantFiled: October 26, 2001Date of Patent: May 25, 2004Assignee: Hewlett-Packard Develpment Corporation, L.P.Inventors: Simon Dodd, Frank Randolph Bryant, Paul I. Mikulan
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Patent number: 6737740Abstract: The present invention provides a semiconductive substrate which includes front and back surfaces and a hole which extends through the substrate and between the front and back surfaces. The hole is defined in part by an interior wall portion and forms an outer conductive sheath. Conductive material is formed proximate at least some of the interior wall portion. Subsequently, a layer of dielectric material is formed within the hole, over and radially inwardly of the conductive material. A second conductive material is then formed within the hole over and radially inwardly of the dielectric material layer. The latter conductive material constitutes an inner conductive coaxial line component.Type: GrantFiled: February 8, 2001Date of Patent: May 18, 2004Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn
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Patent number: 6630743Abstract: A circuitized semiconductor substrate comprising a layer of dielectric material having holes therethrough, a catalyst seed layer lining the walls of the holes along the surface of the dielectric material, and a nickel layer in the openings and a layer of copper above the nickel layer, along with a method for its fabrication. The invention also provides copper-nickel laminate PTH barrels and methods for their fabrication.Type: GrantFiled: February 27, 2001Date of Patent: October 7, 2003Assignee: International Business Machines CorporationInventors: Roy H. Magnuson, Voya R. Markovich, Thomas R. Miller, Michael Wozniak
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Patent number: 6630738Abstract: A package for connecting an integrated circuit to a printed circuit board. The package includes an interconnect having a deflectable cantilever and a solder bump. When the integrated circuit is affixed to the interconnect, the solder bump deflects the cantilever. When the solder bump is heated such that the solder reflows, the cantilever springs toward its non-deflected position and is at least partially absorbed by the reflowing solder.Type: GrantFiled: December 18, 2002Date of Patent: October 7, 2003Assignee: Micron Technology, INCInventor: Timothy L. Jackson
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Patent number: 6627976Abstract: The invention relates to a leadframe for semiconductor packages and a mold for molding the semiconductor package. The leadframe of the invention reduces occurrences of chip-out and floating of a chip paddle upon singulation after encapsulation. The leadframe inner voids define a chip paddle. At least one end of an inner void extends outwardly beyond a dam bar to provide a flow under pathway for encapsulating material when the leadframe is engaged by a top mold. The top mold has a sill that is continuous, e.g. tetragonal in shape, such that encapsulating material must flow under the sill when the top mold is clamping the leadframe. Encapsulating material is flowed into a mold gate of the leadframe and under a portion of the sill to engulf the semiconductor chip within the cavity formed by the top mold and the leadframe.Type: GrantFiled: October 13, 2000Date of Patent: September 30, 2003Assignee: Amkor Technology, Inc.Inventors: Young Suk Chung, Hyung Ju Lee, Jae Hak Yee
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Patent number: 6627997Abstract: In a multi-chip module, a plurality of semiconductor chips are mounted on a single wiring board. Upper surfaces of the semiconductor chips are covered with a single heat spread plate, and the whole space around the semiconductor chips, sandwiched between the wiring board and the heat spread plate, is filled with resin. The semiconductor chips are interconnected through the resin so that any stress exerted on any chips is dispersed. This diminishes the occurrence of cracks caused by stress concentration. Since the semiconductor chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.Type: GrantFiled: January 27, 2000Date of Patent: September 30, 2003Assignee: Hitachi, Ltd.Inventors: Shuji Eguchi, Akira Nagai, Haruo Akahoshi, Takumi Ueno, Toshiya Satoh, Masahiko Ogino, Asao Nishimura, Ichiro Anjo, Hideki Tanaka
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Patent number: 6627959Abstract: A sensor including a p-n junction for subjecting under a reverse electrical bias. A conductive layer is formed across the p-n junction for providing an alternative conductive path across the p-n junction. The conductivity of the conductive layer in the presence of a selected substance in an atmosphere is different than in the absence of the selected substance, wherein the conductivity of the conductive layer is indicative of the presence or absence of the selected substance.Type: GrantFiled: April 16, 2002Date of Patent: September 30, 2003Assignee: Boston MicroSystems, Inc.Inventors: Harry L. Tuller, Richard Mlcak
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Patent number: 6628001Abstract: The present invention provides a die located on a semiconductor wafer. In one embodiment, the die includes a circuit region located within a circuit perimeter of the die. In addition, the die includes a bond pad region located between the circuit perimeter and an outer perimeter of the die. Also the die includes an alignment mark located within the bond pad region.Type: GrantFiled: May 17, 2002Date of Patent: September 30, 2003Assignee: Agere Systems Inc.Inventors: Sailesh Chittipeddi, Keelathur N. Vasudevan
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Patent number: 6624524Abstract: A technique to form a structure with a rough topography (415) in a planarized semiconductor process. The rough topography (415) is formed by creating cored contacts (433). Subsequent process layers may be further stacked on top of the cored contacts in order to augment nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.Type: GrantFiled: October 18, 1999Date of Patent: September 23, 2003Assignee: Altera CorporationInventor: Raminda U. Madurawe
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Patent number: 6621130Abstract: The present invention provides a semiconductor nonvolatile memory in which writing or erasing of storing information can be carried out at a high speed with low consumption power and in which dispersion width of a threshold voltage after writing or erasing is very narrow. A channel region of a memory transistor is divided into two regions of a writing control region and a writing region. The writing control region and the writing region have different threshold voltages. Writing is only carried out in the writing region. The writing control region turns off when the amount of electric charges accumulated in a floating gate reaches a specific value due to writing. The writing control region is used as a switch for a writing operation to automatically stop writing. Accordingly, an involatile memory comprising a memory transistor, in which writing can be carried out at a high speed with low consumption power and which is superior in controlling a threshold voltage after writing or erasing, can be obtained.Type: GrantFiled: May 28, 2002Date of Patent: September 16, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiyuki Kurokawa, Kiyoshi Kato
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Patent number: 6621129Abstract: A MROM memory cell structure for storing multi level bit information is disclosed. First of all, a substrate is provided. The substrate has first and second trenches therein, wherein the first trench is deeper than second trench. A conformnal dielectric layer formed on sidewall and bottom of the first and second trenches. A conductive layer filled in the first and second trenches and on the substrate. A first doped region is formed under the first trench. A second doped region is formed under the second trench. A third doped region is formed in surface of the substrate and between the first and second trenches.Type: GrantFiled: May 24, 2002Date of Patent: September 16, 2003Assignee: Macronix International Co., Ltd.Inventors: Chun-Jung Lin, Ful-Long Ni, Chang-Ju Chen
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Patent number: 6621163Abstract: An electronic device includes an electronic component 2, 3, such as a SAW (=Surface Acoustic Wave) filter 2, 3 having connection areas 4, 5. The filter 2, 3 is sealed off from the environment by means of a cover 6 forming a cavity 7 above the filter 2, 3. According to the invention, the cover 6 is formed by a lacquer layer 6A which is provided, at the location of the filter 2, 3, with an opening 7′ and which is covered with a photoresist layer 6B closing the opening 7′ such that the cavity 7 thus formed has a thickness above zero everywhere above the filter 2, 3. This enables an accurate and stable frequency selection by means of the filter 2, 3 and allows the device according to the invention to be very compact and easy to manufacture. Thus, the device according to the invention is very suitable for use in an application such as a mobile telephone, also after integration of the device with a semiconductor device.Type: GrantFiled: July 3, 2002Date of Patent: September 16, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Johannus Wilhelmus Weekamp, Jorrit Jorritsma, Edwin Petrus Alois Maria Tijssen, Marc Andre De Samber
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Patent number: 6621167Abstract: A metal interconnect structure generally includes a lower-layer metal wiring, an upper-layer metal wiring partially overlapping with the lower-layer metal wiring to define a via region thereof, a dielectric layer disposed between the lower-layer metal wiring and the upper-layer metal wiring, a plurality of via plugs arranged in the dielectric layer within a first area of the via region for electrically connecting the lower-layer metal wiring and the upper-layer metal wiring, and a plurality of first dielectric structures embedded in the upper-layer metal wiring within a second area of the via region, in which the first area does not overlap with the second area.Type: GrantFiled: September 23, 2002Date of Patent: September 16, 2003Assignee: United Microelectronics Corp.Inventors: Chien-Chung Lin, Cheng-Yu Hung, Chien-Mei Wang, Chih-Hung Chen
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Patent number: 6617690Abstract: Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.Type: GrantFiled: August 14, 2002Date of Patent: September 9, 2003Assignee: IBM CorporationInventors: Stephen M. Gates, Timothy J. Dalton, John A. Fitzsimmons
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Patent number: 6617688Abstract: A semiconductor device has a first semiconductor pellet and a second semiconductor pellet. An electrode-forming surface of the first semiconductor pellet on which flat electrodes having flat surfaces are formed and an electrode-forming surface of the second semiconductor pellet on which protruded electrodes are opposed to each other. Also, the flat electrodes and the protruded electrodes are electrically connected to each other. A main component of a conductive material that forms the flat electrode is the same as a main component of a conductive material that forms the protruded electrode. Furthermore, the hardness of the protruded electrode is higher than the hardness of the flat electrode. Therefore, the protruded electrodes and the flat electrodes can be electrically connected to each other with high reliability.Type: GrantFiled: March 27, 2002Date of Patent: September 9, 2003Assignee: NEC Electronics CorporationInventors: Gorou Ikegami, Nobuaki Nagai
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Patent number: 6617678Abstract: There is disclosed a semiconductor device which comprises a first chip-mounting substrate on which at least one semiconductor chip having a plurality of terminals is mounted, and a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, a second chip-mounting substrate which is laminated on the first chip-mounting substrate and on which at least one semiconductor chip is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of a whole arrangement of the relay terminals.Type: GrantFiled: May 16, 2002Date of Patent: September 9, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamazaki, Mitsuyoshi Endo, Chiaki Takubo, Katsuhiko Oyama, Takashi Imoto, Mikio Matsui
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Patent number: 6617684Abstract: An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface attached to the substrate to form a wall around a periphery of the opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface of the semiconductor chip.Type: GrantFiled: August 28, 2002Date of Patent: September 9, 2003Assignee: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark
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Patent number: 6611061Abstract: Ta—Al—N is formed on a semiconductor device structure, such as a wiring line, to prevent interdiffusion between surrounding layers. Ta—Al—N serves as a diffusion between two conductor layers, a semiconductor layer and a conductor layer, an insulator layer and a conductor layer, an insulator layer and a semiconductor layer, or two semiconductor layers. Ta—Al—N also promotes adhesion of adjacent layers, such as two conductor layers, a conductor layer and an insulator layer, a semiconductor layer and a conductor layer, or two semiconductor layers. Ta—Al—N is also useful for forming a contact or electrode. The disclosed Ta—Al—N includes between 0.5% and 99.0% aluminum, between 0.5% and 99.0% tantalum, and between 0.5% and 99.0% nitrogen. A Ta—Al—N layer has a thickness between 50 Å and 6000 Å, and as part of a wiring line, has a thickness between 1% and 25% of the wiring line thickness.Type: GrantFiled: March 7, 2002Date of Patent: August 26, 2003Assignee: Micron Technology, Inc.Inventors: Salman Akram, Scott G. Meikle
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Patent number: 6605842Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).Type: GrantFiled: July 2, 2002Date of Patent: August 12, 2003Assignee: Hitachi, Ltd.Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa