Abstract: A semiconductor device forms a protective diode with a high breakdown voltage at a power terminal of a power IC. An N-type well is formed in a P-type semiconductor substrate, the well electrically connected to a power supply terminal. An N-type channel stopper region is formed in the well. A P-type substrate pickup region is formed outside the well. The distance between the substrate pickup region and the channel stopper region is adjusted such that the breakdown voltage of the parasitic diode is not lower than the rated voltage and not higher than the breakdown voltage of the high voltage PMOSFET fabricated in the well. The protective diode absorbs electrostatic breakdown and electrical noises without an additional circuit protection device or manufacturing process.

Abstract: The present invention provides a design structure of an plated wire of a fiducial mark for a die-dicing package. In the present structure, a cutting line is positioned between each two adjacent ball grid array (BGA) chips. There is configured a solder mask opening at the edge connecting region of the cutting lines. A fiducial mark is positioned in the opening of each BGA chip, wherein the fiducial mark is close to the cutting line and positioned a plated wire therein to pull from the fiducial mark to out the opening and to connect to the plated wire of the cutting line. So as all the plated wires utilizing the coverage of the solder mask can be entirely cut without the pulling problem from the cutter. The present invention provides a new design structure of the plated wire to overcome the burr effect of prior die dicing so as to enhance the product efficiency and decrease the manufacturing cost.

Abstract: An integrated circuit device having an embedded heat slug. The integrated circuit device comprises, in one embodiment, a semiconductor substrate having a frontside surface and backside surface. The semiconductor substrate includes an integrated circuit on the frontside surface. A heat slug is disposed in an opening in the backside surface of the semiconductor substrate adjacent the integrated circuit.

Abstract: An electronic device package includes a modified ball grid array (“BGA”) interconnect substrate upon which a flip-chip device is mounted. The flip-chip device includes one or more high speed input/output solder bumps corresponding to input/output signals having data rates of up to 40 Gbps. A high speed solder bump is directly connected to an interconnect via formed within the BGA substrate, and the via is directly connected to a respective BGA solder ball positioned at an interior point of the BGA solder ball matrix. The BGA substrate is void of BGA solder balls between the designated high speed BGA solder ball and at least one edge of the substrate, thus providing a clear path to the designated high speed BGA solder ball for a high speed conductive trace formed on a printed circuit board.

Abstract: A chip stack comprising at least one base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may each be electrically connected to the first conductive pattern of the base layer such that one of the integrated circuit chip packages is at least partially circumvented by the interconnect frame.

Abstract: An acceleration sensor is disclosed which includes a capacitance-type acceleration detection element mounted on a ceramic base plate. The element comprises a movable electrode mounted between a pair of fixed electrodes. Acceleration of the sensor in a measurement direction causes the movable electrode to move relative to the fixed electrodes and the element has opposite ends in a direction perpendicular to the measurement direction. The acceleration detection element is mounted on the base at a first one of the opposite ends. Accordingly, the mounting surface of the acceleration sensor is parallel to the direction of acceleration to be detected. Thus the acceleration sensor can be surface-mounted on a printed board, and more be easily mounted in an automobile air bag control system or the like.

Abstract: In a method for forming a connection structure in an integrated circuit, a first conducting material is deposited over a substrate and patterned to form a conducting stud in electrical contact with a conducting element of the substrate. A dielectric is formed over the substrate and the conducting stud. A trench is formed in the dielectric to expose a top portion of the conducting stud, and a second conducting material is inlaid in the trench to form wiring in electrical contact with the conducting stud. The electrically conducting element of the substrate may be an element of a semiconductor device or a wiring, contact or via. The first conducting material may be aluminum, and the second conducting material may be copper. The dielectric may be formed as a single layer and may be an organic low-k dielectric. Related connection structures are also disclosed.

Abstract: A structure for selectively programming interconnections between an input contact and an output contact segment in a multilayer semiconductor, comprising a first group of metal segments each being formed on successive layers of the semiconductor and being interconnected by vias, the first group including the output contact segment; a second group of metal segments each formed on successive layers of the semiconductor and being interconnected by vias, the second group including the input contact segment; and means for connecting a metal segment in the first group to a metal segment in a corresponding layer in the second group, thereby connecting the input contact to the output contact.

Abstract: The high-frequency package according to the present invention has a base plate made of copper; a ceramic frame having a space for accommodating a circuit device and mounted on the base plate; and a pattern of circuits developed on the ceramic frame. The base plate and the ceramic frame, and the ceramic frame and the patterned circuits, are both joined together by a DBC technique. According to the present invention, the high-frequency package can be fabricated by a simpler procedure.

Abstract: A contact between a source/drain and a gate is made by making a selected portion of the gate dielectric conductive by an implant into that selected portion of the gate dielectric. The gate material is in a layer over the entire integrated circuit. Areas where gates are to connect to source/drains are indentified and the gate dielectric at those identified locations is implanted to make it conductive. The source/drains are formed so that they extend under these areas of conductive gate dielectric so that at these locations the implanted gate dielectric shorts the gate to the source/drain. This saves area on the integrated circuit, reduces the need for interconnect layers, and avoids the problems associated with depositing and etching polysilicon on an exposed silicon substrate.

Abstract: Embodiments of semiconductor packages containing a stack of at least two semiconductor chips are disclosed, along with methods of making the same. One embodiment includes a substrate, which may be a ball grid array substrate or a metal leadframe. The stack of semiconductor chips is mounted to the substrate. Each semiconductor chip has a plurality of bond pads on an active surface thereof. The bond pads of the first semiconductor chip face corresponding ones of the bond pads of the second semiconductor chip, and are joined thereto through an electrically conductive joint. One of a plurality of bond wires extend from each of the joints to the substrate. Accordingly, pairs of bond pads of the first and second semiconductor chips are electrically interconnected, and are electrically connected to the substrate through the respective bond wire.

Abstract: A semiconductor device with capacitors which have a structure wherein fluctuation in thickness does not occur, even in the case that a dielectric film of low coverage is used. The semiconductor device is provided with adjoining first and second capacitors, wherein the respective capacitor is provided with lower electrode, dielectric film which contacts the top surface of the lower electrode and which has peripheral sidewall surfaces that continue to the peripheral sidewall surfaces of the lower electrode, first upper electrode that contacts the top surface of the dielectric film and a second upper electrode that contacts the top surface of the first upper electrode and the semiconductor device is further provided with a partition insulating film which covers the sidewall surfaces of lower electrode and the dielectric layer between the capacitors so that the second upper electrode contacts the top surface of the partition insulating film.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed. The method for manufacturing the device is capable of performing high angle ion implantation without extending gate-to-gate space.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: A semiconductor device thinner than the past and improved in reliability of electrical connection between semiconductor chips and an interconnection substrate including a polyimide film (insulating plastic film) formed with stud bump through holes, an interconnection pattern formed on one surface of the polyimide film and covering openings of the stud bump through holes at least at that one surface, a first semiconductor chip flip-chip bonded to the interconnection pattern, a second semiconductor chip flip-chip bonded to the other surface of the polyimide film so as to be electrically connected with the interconnection pattern through the stud bump through holes, and solder bumps (external connection terminals) and a method for production of the same by fewer steps than in the past.

Abstract: A method for fabricating a semiconductor interconnect structure having a substrate with an interconnect structure patterned therein, a barrier layer, a pre-seed layer, a seed layer, a bulk interconnect layer, and a sealing layer, and a device thereby formed. The barrier layer is formed using atomic layer deposition techniques. Subsequently, a pre-seed layer is formed to create a heteroepitaxial interface between the barrier and pre-seed layers. This is accomplished using atomic layer epitaxy techniques to form the pre-seed layer. Thereafter, a seed layer is formed by standard deposition techniques to create a homoepitaxial interface between the seed and pre-seed layers. Upon this layered structure further bulk deposition of conducting materials is done. Excess material is removed from the bulk layer and a sealing layer is formed on top to complete the interconnect structure.

Abstract: A semiconductor device including a substrate having a surface on which interconnections are formed, a semiconductor element connected to the interconnections and mounted on the substrate, and a conductive cap for covering the semiconductor element electrically connected to a ground potential. The emission of an electromagnetic wave from the semiconductor element externally of the semiconductor device and malfunctioning of the semiconductor element due to an external electromagnetic wave incident thereon, can be prevented by the conductive cap.

Abstract: The present invention relates to an electronic component formed of an electrically conductive plate and including a plurality of leads 1, 2 each having an island 10 for mounting of a semiconductor chip 3 or having a connecting portion 20 for connection with a wire 4. According to an electronic component X offered by the present invention, at least a set of mutually adjacent leads 1, 2 have their respective mutually facing side surfaces 10a, 20a made non-parallel to each other. Preferably, at least one side surface 20a (10a) of the leads 1, 2 is at least partially curved, folded and/or slanted.

Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.

Abstract: An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface attached to the substrate to form a wall around a periphery of an opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface for the semiconductor chip.