Abstract: A memory system comprises memory devices coupled to a memory controller via a memory interface bus, the memory controller for receiving one or more memory requests via an interconnect. The memory controller tracks utilization of the memory interface bus for reads from the memory devices for a selection of the one or more memory requests during a time window. The memory controller, responsive to detecting utilization of the memory interface bus for reads during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of data to be accessed from the memory devices by at least one read operation, the reduced data size selected from among at least two read data size options for the at least one read operation of a maximum read data size and the reduced read data size that is less than the maximum read data size.

Abstract: Provided are a memory device, a memory system, and a control method performed by the memory system. The control method includes operations of generating, by a first function block of the memory system, a main request comprising a first sub-request for a first operation that is requested by an external source and a second sub-request for a second operation that is dependent upon a processing result of the first operation; processing, by a second function block of the memory system, the first sub-request or the second sub-request; and when a processing result of the first sub-request performed by the second function block is a fail, transmitting, by a third function block of the memory system, abortion information to the first function block in response to the main request, regardless of processing the second sub-request.

Abstract: In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation operation in response to detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

Abstract: In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation in response to detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

Abstract: Embodiments of the presently claimed invention enable a RAID set to appear as if it were initialized immediately after a command to initialize a RAID set is initiated. Typically, a driver or other software in the software stack intercepts the command to initialize the RAID set. The driver then responds to user application programs as if the RAID set initialization is complete, even when it is not. After intercepting the RAID set initialization command, the driver will intercept and respond to data read or write commands as if the RAID set were initialized. The driver or other software will then, typically initialize the RAID set using background tasks. In certain instances, data stored in a non-RAID configuration may be migrated to a RAID configuration during the initialization process.

Abstract: Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode switching to shift data. The WS-SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, a dynamic/static (D/S) mode selector to selectably switch the WS-SRAM cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the WS-SRAM cell accepts shifted data. The WS-SRAM includes a plurality of WS-SRAM cells arranged in an array and a controller to shift data. The method includes switching a storage mode and activating a column selector of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected WS-SRAM cell.

Abstract: In one embodiment, a method for predicting false sharing includes running code on a plurality of cores and tracking potential false sharing in the code while running the code to produce tracked potential false sharing, where tracking the potential false sharing includes determining whether there is potential false sharing between a first cache line and a second cache line, and where the first cache line is adjacent to the second cache line. The method also includes reporting potential false sharing in accordance with the tracked potential false sharing to produce a false sharing report.

Abstract: Methods and systems for cache validation. The cache validation system receives cache requests, and identifies requested cache entries as stale in response to a requested cache entry satisfying a cache invalidation rule. Responsive to a rule insertion request specifying a new rule that, when added to an existing set of rules, would exceed a rule-set capacity limitation, a revised rule is generated that is at least as broad as the union of one or more subsumable rules. Each of the one or more subsumable rules is either the new rule or a rule in the existing set of rules. The set of rules is then updated, without exceeding the capacity limitation, to include the revised rule and to exclude the one or more rules subsumed into the revised rule. If not included in the revised rule, the new rule is included in the updated set of rules.

Abstract: Methods, apparatuses, systems, and computer-readable media for dynamically improving performance of a host memory controller and a hosted memory device are presented. According to one or more aspects, a memory controller may establish a data connection with a memory device. The memory controller may perform a first write operation of a plurality of write operations to the memory device using a first block size. Subsequently, the memory controller may perform a second write operation of the plurality of write operations to the memory device using a second block size different from the first block size. The memory controller then may determine an optimal value for a block size parameter based at least in part on the plurality of write operations. Thereafter, the memory controller may use the optimal value for the block size parameter in performing one or more regular tasks involving the memory device.

Abstract: A storage controller receives a write command with respect to a track, from a host. A first process determines that the track is a source track and also determines that at least one corresponding target track is in an incremental copy relation to the source track. A second process is generated to modify a target change recording structure, where the second process executes in parallel with the first process.

Abstract: An information management system according to certain aspects may determine whether snapshot operations will work prior to executing them. The system may check various factors or parameters relating to a snapshot storage policy to verify whether the storage policy will work at runtime without actually executing the policy. Some examples of factors can include: availability of primary storage devices for which a snapshot should be obtained, availability of secondary storage devices, license availability for snapshot software, user credentials for connecting to primary and/or second storage devices, available storage capacity, connectivity to storage devices, etc. The system may also check whether a particular system configuration is supported in connection with snapshot operations. The result of the determination can be provided in the form of a report summarizing any problems found with the snapshot storage policy.

Abstract: Methods and systems for synchronous replication of data are provided. A master intelligent storage adapter operating within a cluster having a slave intelligent storage adapter receives a plurality of write requests; generates a first input/output (I/O) request for storing the data for the plurality of write requests at a first storage device; and generates a second I/O request for a replication module executed by a computing device for synchronously storing the data at a second storage device. The computing device initiates a synchronous replication operation to replicate the data for the plurality of write requests at the second storage device.

Abstract: A method, non-transitory computer readable medium, and device that prefetchs includes identifying a candidate data block from one of one or more immediate successor data blocks. The identified candidate data block has a historical access probability value from an initial accessed data block which is higher than a historical access probability value for each of the other immediate successor data blocks and is above a prefetch threshold value. The identifying is repeated until a next identified candidate data block has the historical access probability value below the prefetch threshold value. In the repeating, the identifying next immediate successor data blocks is from the previously identified candidate data block and the historical access probability value for each of the next immediate successor data blocks is determined from the originally accessed data block. The identified candidate data block with the historical access probability value above the prefetch threshold value is fetched.

Abstract: Dynamic/static random access memory (D/SRAM) cell, block shift static random access memory (BS-SRAM) and method using the same employ dynamic storage mode and dynamic storage mode switching to shift data. The D/SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, and a dynamic/static (D/S) mode selector to selectably switch the D/SRAM cell between the dynamic storage mode and a static storage mode. The BS-SRAM includes a plurality of D/SRAM cells arranged in an array and a controller to shift data from an adjacent D/SRAM cell in a second row of the array to a D/SRAM cell in a first row. The method includes switching the mode of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected D/SRAM cell.

Abstract: According to one aspect of the present disclosure, a system and technique for capacity forecasting is disclosed. The system includes a host having a processor unit and a memory. Resource data stored associated with an environment is stored in the memory, the resource data comprising inventory information of applications, processing resources and storage resources of the environment. A ledger module is executable by a processor unit to: create a capacity-associated transaction; identify and link at least one of an application, processing resource and storage resource to the transaction from the resource data; determine an initiation time and duration associated with the transaction; and forecast a change in capacity of at least one linked storage resource for the transaction and a time of the change in capacity.

Abstract: According to one aspect of the present disclosure, a method and technique for capacity forecasting is disclosed. The method includes: storing, in a memory, resource data associated with an environment, the resource data comprising inventory information of applications, processing resources and storage resources of the environment; and providing a ledger module executable by a processor unit to: create a capacity-associated transaction; identify and link at least one of an application, processing resource and storage resource to the transaction from the resource data; determine an initiation time and duration associated with the transaction; and forecast a change in capacity of at least one linked storage resource for the transaction and a time of the change in capacity.

Abstract: A storage controller receives a write command with respect to a track, from a host. A first process determines that the track is a source track and also determines that at least one corresponding target track is in an incremental copy relation to the source track. A second process is generated to modify a target change recording structure, where the second process executes in parallel with the first process.

Abstract: A first data structure stores indications of storage locations that need to be copied for forming a consistency group. A second data structure stores indications of new host writes subsequent to starting a point in time copy operation to form the consistency group. Read access is secured to a metadata storage area and a determination is made as to whether the second data structure indicates that there are any new host writes. In response to determining that the second data structure indicates that there are new host writes, write access is secured to the metadata storage area, the first data structure is updated with contents of the second data structure to determine which additional storage locations need to be copied for formation of a next consistency group, and the second data structure is updated to indicate that that the second data structure is in an initialized state.

Abstract: A first data structure stores indications of storage locations that need to be copied for forming a consistency group. A second data structure stores indications of new host writes subsequent to starting a point in time copy operation to form the consistency group. Read access is secured to a metadata storage area and a determination is made as to whether the second data structure indicates that there are any new host writes. In response to determining that the second data structure indicates that there are new host writes, write access is secured to the metadata storage area, the first data structure is updated with contents of the second data structure to determine which additional storage locations need to be copied for formation of a next consistency group, and the second data structure is updated to indicate that that the second data structure is in an initialized state.

Abstract: A type of conditional probability fetcher prefetches data, such as for a cache, from another memory by maintaining information relating to memory elements in a group of memory elements fetched from the second memory. The information may be an aggregate number of memory elements that have been fetched for different memory segments in the group. The information is maintained responsive to fetching one or more memory elements from a segment of memory elements in the group of memory elements. Prefetching one or more remaining memory elements in a particular segment of memory elements from the second memory into the first memory occurs when the information relating to the memory elements in the group of memory elements indicates that a prefetching condition has been satisfied.