Abstract: System and techniques for rebuilding a redundant secondary storage cache including a first storage device and a second storage device are described. A metadata entry indicative of a validity of a portion of information stored by a first storage cache device and associated with a region of a primary storage device is received. When the validity of the portion of information associated with the region of the primary storage device is established, a region lock is requested on the region of the primary storage device associated with the portion of information stored by the first storage cache device. Then, the portion of information and the corresponding metadata entry associated with the region of the primary storage device is copied from the first cache storage device to a second storage cache device to rebuild the second storage cache device.

Abstract: An electronic apparatus includes a memory control part that carries out allocation and deallocation of a memory area in a memory space; a memory reorganization part that carries out a reorganization process of moving the memory area allocated by the memory control part and creating a contiguous free space in the memory space; and a reorganization control part that causes the reorganization part to carry out the reorganization process in a case where a first predetermined condition is met, and does not cause the reorganization part to carry out the reorganization process in a case where a second predetermined condition different from the first predetermined condition is met.

Abstract: A data processing device is provided that facilitates cache coherence policies. In one embodiment, a data processing device utilizes invalidation tags in connection with a cache that is associated with a processing engine. In some embodiments, the cache is configured to store a plurality of cache entries where each cache entry includes a cache line configured to store data and a corresponding cache tag configured to store address information associated with data stored in the cache line. Such address information includes invalidation flags with respect to addresses stored in the cache tags. Each cache tag is associated with an invalidation tag configured to store information related to invalidation commands of addresses stored in the cache tag. In such embodiment, the cache is configured to set invalidation flags of cache tags based upon information stored in respective invalidation tags.

Abstract: An information processing system includes: CPUs; storage devices; switches; dummy storage devices which are with respective storage devices and each of which sends, when receiving an identifying information request, its own identifying information back to a sender of the identifying information request; and dummy CPUs which are associated with respective CPUs and each of which tries to, when receiving an instruction for acquiring identifying information from a dummy storage device, acquire the identifying information of the dummy storage device by transmitting the identifying information request, and sends the identifying information as response information back to a sender device of the acquiring instruction.

Abstract: A memory system that includes a memory device and a memory controller. The memory device includes a plurality of memory cells, and a first storage unit configured to store information about a weak cell from among the plurality of memory cells. The memory controller is configured to transmit an operation command signal to the memory device, and control an operation of the memory device by using the information about the weak cell provided from the first storage unit. If the operation command signal is related to an operation to be performed using a first of the memory cells and the first memory cell is the weak cell, the memory device is configured to transmit the information about the weak cell to the memory controller.

Abstract: Expanding capacity of a logical volume is described. In an example a logical volume is described by a global metadata unit and a plurality of local metadata units. The global metadata unit includes a description of the logical volume, a list of the plurality of local metadata units, and ranges of logical blocks of the logical volume corresponding to the plurality of local metadata units. Each of the local metadata units includes a description of a local RAID set and a range of logical blocks on the local RAID set. When a new drive is to be added to the logical volume to increase capacity, a new local metadata unit is created. The new local metadata unit includes a description of a new local RAID set to be added to the RAID volume and a range of logical blocks on the new drive. The new local metadata unit is added to the global metadata unit to expand the logical volume to incorporate the new local RAID set.

Abstract: A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations.