Abstract: A circuit to implement a multi-channel parallel to serial conversion and a multi-channel serial to parallel conversion in one minimal RAM Matrix. The number of RAM cells (bits) needed is equivalent to the number of Flip-Flops used in a standard shift register and holding register implementation.

Abstract: A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.

Abstract: Apparatus and method for determining the lengths of a plurality of variable length encoded data values included in a data stream within a single clock cycle. The apparatus includes a shifter for receiving the data stream. The shifter is responsive to a shift control signal for transmitting a subset of the plurality of variable length encoded data values. A first length decoding mechanism is coupled to receive the subset of the plurality of encoded data values. The first length decoding mechanism performs a first decoding operation to determine the length of a first one of the encoded data values in the subset. A second length decoding mechanism is also coupled to receive the subset of the plurality of encoded data values. The second length decoding mechanism performs a second decoding operation to individually determine the length of a second one of the encoded data values in the subset. The second encoded data value immediately follows the first encoded data value in the subset.

Abstract: A digital-to-analog conversion method and interpolating digital-to-analog converter for a data modulation system which reduces the spurious energy content of the output signal by an order of magnitude to thereby permit use of a less complex reconstruction filter to smooth the analog output. The process is a two step charge redistribution with feedback to interpolate between samples. DC offset is minimized by using double sampling techniques which permit a fully held signal between interpolation samples. A first conversion stage converts the first n bits of an N bit data signal received at an input rate to a first output value, and a second conversion stage converts the remainder of the N bits and combines signals from the two conversion stages to provide a combined output to an interpolation stage which provides an interpolated output at an interpolation output rate. A feedback circuit provides the interpolated output to an input of the second conversion stage.

Abstract: A new self calibration technique for pipe line A/D converters is presented. It consists of calibration by correcting the reference voltage to each stage by means of a tunable MOSFET attenuator. This simplifies the calibration circuit in each stage and shifts most of the calibration task to a hardware that is shared by all the stages.

Abstract: A pulse width modulated, digital-to-analog converter (PWM DAC) that includes a pulse generator for generating width modulated pulses in accordance with a digital control value is set forth. The generator includes a clock for generating a clocking signal, a counter responsive to the clocking signal for generating repeating sequences of N-bit counts, each sequence representing a count interval. The PWM DAC further includes a bit rotator for receiving the sequences of N-bit counts and for rotating the bit position of at least a most significant one of N-bits. A latch holds a digital control value, whereby a comparator compares the digital control value with each one of the rotated bit counts to put out the width modulated pulses during the count interval. The rotated bit counts increases the frequency of the comparator, in a substantially linear manner, such that subsequent filtering can be accomplished with minimum time requirements.

Abstract: A variable length decoder which is particularly suitable for decoding digital video data for HDTV. The variable length decoder operates to decode in parallel qualifying code words, such as payload data in an MPEG data stream, during a single clock cycle, and operates to decode singular non-qualifying code words, such as setup data in the MPEG data stream, during a single clock cycle. Since the payload data constitutes approximately 95% of the MPEG data stream, the throughput of the VLD of the present invention is significantly higher than that of the presently available VLDs, at a clock rate that is significantly lower than that of the presently available VLDs.

Abstract: A register circuit for holding an analog input voltage includes a plurality of thresholding circuits of stepwise thresholds, an integrating circuit for integrating outputs of the thresholding circuits and a switching circuit for alternatively inputting an output of the integrating circuit or the analog input voltage to the thresholding circuits as the input voltage of the capacitive coupling.

Abstract: An A/D converter including a first inverter having a linear characteristic and receiving an analog input voltage, a first quantizing circuit for quantizing the analog input voltage, a capacitive coupling to which an output of the first inverter and the first quantizing circuit are inputted, a second inverter receiving an output of the capacitive coupling and having the same characteristic of the first inverter, and a second quantizing circuit for receiving and quantizing an output of the second inverter. The A/D converter performs successive steps of quantizing/digitizing so as to achieve A/D conversion.

Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

Abstract: An analog to digital converter provides a device for characterizing, in digital terms, a first quantity having a magnitude which varies as a function of a second quantity. An output signal is generated having more than two values, the output signal indicating the magnitude of the first quantity in comparison to a reference level and the change in the magnitude of the first quantity as a function of the second quantity.

Abstract: In a circuit at least one of the signals (u?t! or i?t!) is transmitted to a signal input of a sigma-delta modulator operated at a first clock frequency (1/T.sub.S) the output of which is connected to at least one of two signal inputs of a multiplication/addition element (3). The arrangement is used for example in electricity counters and makes it possible to calculate sums of products by means of simple shift and algebraic adding operations while maintaining closely the precision achievable with a classic multiplication. The arrangement is especially advantageous if the multiplications are done on a semiconductor chip.

Abstract: An analog to digital converter for the conversion of an analog input signal to a digital output code of n bits has a plurality of voltage references created in a voltage reference generator that divides the total range of voltage of the conversion input into increments of voltage equal to the smallest increment of resolution. The n bits of digital output are divided into most significant bits and least significant bits. The most significant bits are encoded from a set of digital signals that are formed in a set of coarse comparators, that compare the analog input signal with a subset of the voltage references representing the coarse range. The digital code that is the output of the coarse comparators is used to determine the selection of the subset of the plurality of the voltage references that are the fine voltage references. The least significant bits are encoded from a set of digital signals that are formed in a set of fine comparators that compare the analog input signal to the fine voltage references.

Abstract: A sub-ranging analog to digital converter utilizes open loop differential gain amplifiers and analog switches to implement a pipeline. Each stage of the converter contains two fine range transfer amplifiers, sampling switches and hold capacitors, a low resolution sub-range analog to digital converter and a resistive ladder. The sampling switches behave as a digital to analog converter. Each stage then converts the held analog value to a digital code, which is used to operate the transfer switches to select the proper sub-range result for the next stage. The transfer switches are analog switches that perform the function of both the sampling and the sub-range transfer. The interstage amplifiers are simple open loop differential amplifiers with a rather imprecise absolute gain. Because the reference and the signal are both amplified by this imprecise gain, both the reference and the signal are amplified by the same amount.

Abstract: A digital to analog converter that includes circuitry that converts sequences of positive and negative digital data samples into electrical currents and current mirror circuitry that generates an analog waveform by combining and amplifying the electrical currents.

Abstract: An A/D converter includes a three-state comparator for detecting a higher state, a lower state and a equal state of a sampled analog signal with respect to a sequence of reference signals which are supplied from a counter or register after D/A conversion. After the equal state is detected, the D/A converter and the three-state comparator are stopped for power saving. The A/D converter further includes a frame memory and a control section which provide the counter or register with an initial code for each conversion cycle based on the last code of the previous conversion cycle constituting the previous digital output of the A/D converter. The A/D converter well follows the sequential change of the input level between the conversion cycles.

Abstract: Disclosed is a method and a device for compensating the DC offset (dU) of a D/A converter (2), particularly in the base frequency modulator of a mobile phone. The method and the device use an error correction register (5), whose value is changed on the basis of the DC offset, and which is added to each signal sample to be converted for compensating the DC offset. The value of the error correction register (5) is changed in a testing mode so that a preset control value is fed into the D/A converter (2), corresponding to the zero voltage of the output of an ideal D/A converter; the voltage values of outputs of a differential output pair (2a, 2b) arranged in connection with the D/A converter (2) are compared to verify the polarity of the voltage difference (dU) of the outputs and the polarity, i.e.

Abstract: An analog-to-digital (A/D) converter using a charge-coupled device (CCD) for converting analog data to digital data, the CCD including a plurality of gates with potential wells, the number of gates corresponding to a number of bits of the digital data, and a size of each potential well corresponding to a given significant bit and being one-half the size of the potential well corresponding to the next most significant bit. The charges of an input analog signal are transmitted to respective potential wells. A plurality of driving circuits apply a voltage to the respective potential wells and output the charges stored in the respective potential wells as digital data.

Abstract: In a computer implemented method for encoding digital values that are arranged in a successively increasing order, a delta value is determined for each pair of immediately successive values. The delta values are the differences between the pair of immediately successive values. For each delta value which can be encoded as a single byte, a logical zero is stored in the least significant bit of the single byte, and the delta value is stored in the most significant bits of the single byte. Otherwise, for each delta value which must be encoded as a plurality of bytes, a logical one is stored in the least significant bit of the first byte of the plurality of bytes, and a first portion of the delta value is stored in the most significant bits of the first byte. In this case, a logical zero is stored in the most significant bit of the next byte, and a next portion of the delta value is stored in the least significant bits of the next byte.

Abstract: An analog-to-digital (A/D) converter is provided for converting an analog signal to a digital signal, wherein the digital signal is corrected such that it does not contain DC offset. The A/D converter preferably comprises a delta-sigma modulator and an offset compensation circuit. The offset compensation circuit is coupled to the output of the modulator or, according to another embodiment, to the output of a noise cancellation circuit. The offset compensation circuit can calibrate a single bit output from the modulator or a multi-bit output from the noise cancellation logic. In the former instance, the offset compensation circuit includes an up/down counter and register; in the latter instance, the calibration circuit includes an accumulator. The offset compensation circuit counts or accumulates a digital representation of DC offset.