Abstract: An analog-to-digital converter includes a reference voltage generator for dividing a voltage between first and second reference voltages by a plurality of resistors serially connected therebetween and providing a plurality of reference voltages at each connecting point of the resistors; a plurality of emitter-coupled comparators for respectively generating a comparative signal by comparing the reference voltages with an analog input signal; and a plurality of constant current sources for respectively supplying an input bias current to each reference voltage input terminal of the emitter-coupled comparators.

Abstract: A new differential ladder/comparator circuit reduces settling time delays in parallel analog to digital converters. A parallel analog-to-digital converter (ADC) includes a pair of differential resistor ladders having their taps connected to a group of comparators. The comparators produce digital "thermometer" scale outputs corresponding to analog signals impressed upon the differential ladders. By employing double-value resistors to form the "rungs" of the ladders and by connecting the comparators to the ladder taps in a way that increases the number of comparator inputs connected to the ladders' lower-order taps and decreases the number of comparator inputs connected to the ladders' higher order taps, the input impedance presented by the ladder/comparator combination is reduced in comparison with conventional differential ladder parallel ADCs.

Abstract: In a dual resistor string digital-to-analog converter, current biasing is used to isolate a first resistor string from a second resistor string. The first resistor string consist of multiple first resistors, and a first switch network responsive to the MSBs selectively couples the second resistor string in parallel to any one first resistor within the first resistor string. To prevent the second resistor string from drawing current from the first resistor string, a current source feeds a bias current into the second resistor string and a current drain draws the bias current from the second resistor string. The bias current is adjusted such that the voltage drop across the whole of the second resistor string is equal to the voltage drop across any one first resistor within the first resistor string.

Abstract: An input data sequence is divided into fixed-length source segments, and each source segment is predicted from preceding data. The data are coded as a sequence of coded segments, each designating a non-negative number of correctly predicted segments and a non-negative number of literal segments. The literal segments are inserted into the coded data among the coded segments. The coded data are decoded by decoding each coded segment, predicting the designated number of correctly predicted segments from previously decoded data, and copying the literal segments. The length of the coded segments may vary according to the number of consecutive correctly predicted segments. The prediction rule, or the original data, may be modified under certain conditions, in order to increase the predictability of the source segments.

Abstract: An N bit (where N is an integer) converter having separately formed voltage dividing resistance regions includes a semiconductor substrate of a first conductivity type. (N+1) well regions of a second conductivity type are each formed separately on the semiconductor substrate and an input resistance region of the first conductivity type having a high concentration of impurities is formed in a first well region of the (N+1) well regions. (N-1) ladder resistance regions of the first conductivity type having a high concentration of impurities respectively are formed in (N-1) well regions, each resistance of the (N-1) ladder resistance regions being approximately two times greater than a resistance of the input resistance region. An output resistance region of the first conductivity type having a high concentration of impurities is formed in an (N+1)th well region of the (N+1) well regions, a resistance of the output resistance region being approximately equal to the resistance of the input region.

Abstract: A database record compression system compresses data with frequency priority. The system has a formal dictionary for storing compressed strings and entry numbers corresponding to the compressed strings. A temporary dictionary compresses and stores strings of the plurality of strings input from an input file which are not stored in the formal dictionary. The system initializes all entries of the temporary dictionary when a number of registrations in the temporary dictionary reaches a predetermined number of initializations. In the system, an occurred string is registered in the formal dictionary when a frequency of occurrence of the string at the temporary dictionary reaches a predetermined number of times.

Abstract: An analog-to-digital converter includes a coarse conversion circuit, a fine conversion circuit, a scaling circuit, and a logic circuit. An analog input signal is applied to the scaling circuit which provides a scaled signal. The scaled signal is applied to the fine conversion circuit which provides a digital control signal. The digital control signal is applied to the coarse conversion circuit for initializing the coarse conversion circuit. Thereafter, the analog input signal is applied to the initialized coarse conversion circuit which provides a first digital code and a reference signal associated with the first digital code. A remainder signal is determined at least in part by the difference between the analog input signal and the reference signal. The remainder signal is applied to the fine conversion circuit which provides a second digital code. The logic circuit determines a digital output signal, representing the analog input signal, in response to at least the first and second digital codes.

Abstract: A method of decoding Huffman-encoded words at the rate of one per clock cycle. The encoded words are formed into two strings of bits, one for odd numbered code and one for even numbered code, and two decoders in parallel are used, each first shifting in a number of coded bits during a first clock period, and converting the Huffman code to data on a second clock period. The two parallel decoders are timed so that the shift cycle of one decoder occurs at the same time as the conversion cycle of the other. Finally, the two streams of decoded data words are combined into one stream. The result is one output data word per clock cycle.

Abstract: An apparatus and a method for controlling a mode of operation of a data converter is based on a length of an input word signal to the data converter. The apparatus includes a bit counter that counts the number of bits in the word received by the data converter and provides a word length signal corresponding to the number of bits in the word, and a mode selector that receives the word length signal and selects an operational mode of the data converter based on the word length signal. The method includes steps of counting the number of bits in the word, and selecting a mode of operation of the data converter based on the number of bits in the word.

Abstract: An analog-to-digital converter includes a comparator for comparing a voltage output by a digital-to-analog converter with an input analog voltage at each bit of an n-bit word. The input analog voltage and the analog output voltage of the digital-to-analog converter are alternatingly used as the reference in the comparison, i.e., for every other bit of the n bits. A one-bit result-of-comparison signal indicative of the result of the comparison is output for each of the n bits. Only alternating result-of-comparison signals are inverted and the inverted and non-inverted result-of-comparison signals are stored in a successive approximation register as the converted digital signal and are supplied to the digital-to-analog converter for use in the comparison.

Abstract: In a demultiplex circuit and an analog-to-digital converter using the demultiplex circuit, since the reset means for controlling the phase of the second clock output from the frequency divider circuit is provided, it is possible to establish the phase of the second clock to establish the output timing of the demultiplex circuit. In addition, since the reset means for controlling the phase of the second clock output from the frequency divider circuit, it is also possible to establish the phase of the second clock to establish the output timing of the analog-to-digital converter.

Abstract: A digital-to-analog conversion circuit includes a first reference voltage generation circuit for generating a plurality of first reference voltages, a plurality of second reference voltage generation circuits for generating a plurality of second reference voltages created by dividing a difference in potential between adjacent two of the first reference voltages, a first selective control circuit for, upon receiving a first digital input signal group, selecting one of the first reference voltages and applying the selected one to a specified one of a plurality of signal lines during a first period, and selecting all of second reference voltages generated in one of the plurality of second reference voltage generation circuits and applying all the selected second reference voltages to signal lines other than the specified signal line, respectively, during a second period succeeding the first period, and a second selective control circuit for, upon receiving a second digital input signal group, applying a voltage

Abstract: A method of self calibration for a segmented digital-to-analog converter is provided. The segmented digital-to-analog converter converts a digital input code to an analog output consisting of an analog output step and an analog calibration factor. The method comprises the step of determining a trim value for each segment of a segmented DAC. The method continues by storing the trim values in memory. Then, the trim values for a plurality of segments preselected to be enabled by a given digital input signal are summed, thereby producing a digital calibration factor associated with each given digital input signal. Last, storing each digital calibration factor in memory at an address corresponding to the associated digital input signal.

Abstract: A data compression algorithm in which a word is assigned a code value according to the frequency of the word occurring, for example, in the English language. The code value contains a length field and a code field. The number of bits used to represent the length field is fixed, whereas the length of the code field is variable. The code field can be assigned values between 0b0 and 0b11111111111111. The value 0b0 is assigned for the word having the greatest probability of occurring and the value 0b11111111111111 is assigned for the word having the least probability of occurring. The value of the length field is equal to the number of bits contained in the code field. The code values are stored in a dictionary with their corresponding words. If it is determined that an input word does not exist in the dictionary, then the length field is assigned the value 0b0000 and the word is represented in its ASCII code.

Abstract: A DAC converts a sequence of digital codewords into an approximately piecewise linear analog waveform that follows rising and falling edges between plateau levels. The DAC processes, in parallel, each bit of the codewords to produce component waveforms that are weighted according to their bits significance and summed together to produce the piecewise linear analog waveform. Waveform shaping circuits control the rise and fall times of each component waveform so that the analog waveform's rising and falling edges settle to within a desired error bound of a linear output ramp whose slope is a function of the difference between successive codewords and the rise or fall times. The rise and fall times are preferably approximately the same. Limiting switches control the plateau levels of the component waveforms so that the analog waveform's plateaus settle to within the desired error bound of the ideal values represented by the codewords.

Abstract: An integrated circuit is disclosed including an analog-to-digital (A/D) converter having an offset source for providing an offset signal; and a first reference array including a plurality of cells for generating a first output signal from an input signal and the offset signal, for generating a second output signal from the offset signal, and for generating an A/D output signal from the first and second output signals.

Abstract: An integrated circuit for a disk drive that includes a sucessive-approximation analog-to-digital converter (ADC) with a two-stage digital-to-analog converter (DAC) and may also include a servo demodulator. The circuit may be implemented in a basic or pure-digital CMOS chip because the ADC includes no precision analog elements such as resistors and capacitors. The first DAC stage operates on the most significant group of bits, and the second DAC stage operates on the least significant group of bits. The DAC includes a reference current source. The first DAC stage is a multiplying DAC that multiplies the reference current in response to its digital input, and the second stage is a dividing DAC that divides the reference current in response to its input. The DAC also includes a current summer, such as a resistor, that receives the output current of each stage and provides the voltage that corresponds to the sum of the currents to a comparator. The comparator output controls a successive-approximation register.

Abstract: A signal converter for converting a bi-phase-level data stream to non-ret-to-zero-level data. The bi-phase-level data stream is input to a detector circuit. When the detector circuit detects a high level for more than half of a bit period, the detector circuit provides a logic zero pulse at a state S7. If the high level is not at the logic one state for a sufficient time period the detector circuit will not reach state s7. If the time period is to short than the detector circuit is reset to state s0. This high level pulse occurs whenever the second half of a bit period is high followed by a high in the first half of the following bit period. A sample is taken on the first half of every bit period. A low at the detector circuit keeps the detector circuit at state s0. A clock signal generating circuit receives the logic zero pulse and then proceeds through its states s0-s10. When state S1 is reached a clock pulse is provided by the clock signal generating circuit.

Abstract: The present invention is intended to realize an analog signal sampling circuit constructed with field-effect transistors wherein errors caused by parasitic capacitance or gate conductance in a switch device is reduced. The sampling circuit of the invention comprises an inverting amplifier, a capacitor, a first switch for selecting a reference voltage Vref or a target signal Vin for input to the capacitor, and a second switch for opening or closing the connection between the input and output of the inverting amplifier, and produces an output in proportion to the difference between the target signal Vin and reference voltage Vref held in the capacitor, the sampling circuit being characterized by the inclusion of a voltage converting circuit whereby the operating voltage of the clock signal applied to the gate of the field-effect transistor forming the second switch is converted to a voltage related to the self-bias level of the inverting amplifier.

Abstract: A device for coding a series of symbols based on a multi-level arithmetic coding scheme includes a coding unit for coding the symbols based on frequency of occurrence of the symbols and orders of the symbols according to the frequency of occurrence, a context holding unit for storing the frequency of occurrence and the orders, a context updating unit for updating the frequency of occurrence and the orders upon receiving a control signal, and a controlling unit for sending the control signal when one of the symbols is coded and a cumulative frequency is less than a predetermined value, wherein the cumulative frequency is a sum of the frequency of occurrence for all of the symbols.