Abstract: A variable length coder is disclosed having a ping-pong zig-zag RAM, a zig-zag FIFO and a variable length integer (VLI), variable length code word (VLC) mixer. The ping-pong zig-zag RAM has a first RAM for processing each odd ordinalled block of the inputted sequence of blocks and a second RAM for processing each even numbered block of the inputted sequence of blocks. The zig-zag FIFO has a comparator circuit, a counter and a FIFO. The comparator circuit is for determining whether or not an inputted coefficient is equal to zero. If the coefficient is non-zero, it is stored in the FIFO. If the coefficient equals zero, the counter increments a count maintained therein. The counter counts the number of zeros in each continuous sequence of zero coefficients in each block and outputs the count for each sequence of zeros for storage in the FIFO. The VLI,VLC mixer has a decoder for receiving the length of a VLC for each VLI,VLC pair and for outputting a mask word depending on the inputted VLC length.

Abstract: The process of converting a digital data word having N-bits into an analog voltage value includes decrementing or incrementing a counter word (B) having N-bits from a respective maximum or minimum value to form a series of decremented or incremented values, synchronizing the decrementing or incrementing of the counter word (B) to a time course of an analog reference voltage (U.sub.ramp) having a ramp-shaped time dependence, evaluating a logical connection function of the decremented or incremented values of the counter word (B) with a digital data word (A) to determine when one of the decremented or incremented values of the counter word (B) is equal to a complement of the digital data word (A) and setting an output analog voltage value (U.sub.column) equal to the analog reference voltage (U.sub.ramp) as soon as the decremented or incremented value of counter word (B) equal to the complement of data word (A) is reached.

Abstract: A method of self calibration for a segmented digital-to-analog converter is provided. The segmented digital-to-analog converter converts a digital input code to an analog output consisting of an analog output step and an analog calibration factor. The method comprises the step of determining a trim value for each segment of a segmented DAC. The method continues by storing the trim values in memory. Then, the trim values for a plurality of segments preselected to be enabled by a given digital input signal are summed, thereby producing a digital calibration factor associated with each given digital input signal. Last, storing each digital calibration factor in memory at an address corresponding to the associated digital input signal.

Abstract: N-bit digital signals are transformed into M-bit digital signals (M>N), the N-bit signals being obtained by converting an analog signal into digital signals. Detected are transition points on a time axis and intervals between the transition points at which successive digital signals of the N-bit signals vary. (M-N) bit additional signals are generated which correct errors of the N-bit signals within a range of .+-.0.5 least significant bit of the N-bit signals in response to the transition points and the intervals. The additional signals are delayed so as to correspond to least significant bit of the N-bit signals. The delayed additional signals are combined with the N-bit signals to generate the M-bit signals. Instead of the transition points and intervals, detected are transition patterns of successive digital signals of the N-bit signals over transition points. (M-N) bit additional signals are generated which correct errors of the N-bit signals within a range of .+-.0.

Abstract: According to the present invention, a modification of standard successive approximation analog to digital converter circuitry may be utilized to measure an unknown analog value and to produce a digital value after conversion that automatically contains an offset value with respect to a given measurement range. The offset achieved by the successive approximation A/D converter is proportional to an external reference which is used as the reference for the successive approximation A/D converter. The digital value produced according to the present invention is not representative of a raw measurement value but rather is representative of a value with respect to a given measurement range; thus, a digital value of 0 may indicate the minimum value of a given measurement range rather than a value of 0 Ohms, 0 volts, or 0 Amps. This may be expressed in equation form where the desired conversion value is represented by:k(X.sub.unknown -X.sub.offset)where k is a constant, X.sub.

Abstract: An A/D converter block A/D1 converts an analog input signal Vin to a digital signal and outputs its D/A output. First SH/SUBT7, 8 sample the signal Vin and a voltage VRM at the same timing with said A/D conversion and output the results of subtraction of the respective sampling values and the D/A output during holding, respectively. The both results of subtraction are several tens mV and there is no need of taking account of the linearity of a differential amplifier DIFF11. During the sampling, a circuit SHR1 outputs the differential voltages between each reference tap voltage taken out from specific 2 points of the ladder-type resistor in the A/D converter block A/D1 and the voltage VRM while a differential amplifier DIFF12 applies the reference voltages to the next A/D converter block A/D2. Such operations are performed in each stage. Thus, it becomes possible to make any S/H circuit and amplifier of excellent linearity in the first stage unnecessary to reduce the electric power consumption.

Abstract: In a parallel to serial converter, data is inputted in parallel to a set of latches in a cycle of an inputted first clock signal. A second clock signal having a 50% duty cycle is generated according to the inputted first clock signal. The second clock signal is delayed to output a third clock signal and a switching unit selects and outputs the latched data in response to the second and third clock signals.

Abstract: A dual stage data lossless compressor for optimally compressing bit mapped imaged data. The first stage run length compresses data bits representing pixel positions along a scan line of a video image to data units of fixed length. The units alternate to represent runs of alternate video image data values. The run length compressed data units are subject to second stage compression using a sliding window Lempel-Ziv compressor. The output from the Lempel-Ziv compressor includes raw tokens of fixed length and compressed tokens of varying lengths. The combination of a run length precompressor and a sliding window Lempel-Ziv post compressor, in which the run length compressor output is a succession of data units of fixed length, provides an optimum match between the capabilities and idiosyncracies of the two compressors, and related decompressors, when processing business form data images.

Abstract: According to the present invention, standard analog to digital converter circuitry may be utilized to measure an unknown analog value and to produce a digital value after conversion that automatically contains an offset value with respect to a given measurement range. The digital value produced according to the present invention is not representative of a raw measurement value but rather is representative of a value with respect to a given measurement range; thus, a digital value of 0 may indicate the minimum value of a given measurement range rather than a value of 0 Ohms, 0 volts, or 0 Amps. This may be expressed in equation form where the desired conversion value is represented by:k(X.sub.unknown -X.sub.offset)where k is a constant, X.sub.unknown is the unknown analog value being measured, and X.sub.offset is the offset value. X.sub.offset the offset value may or may not be equal to a reference value.

Abstract: A method of performing Ziv-Lempel type data compression while preserving in the compressed records any sort ordering of the uncompressed records. The method assigns the necessary ordered numbering to the code words for character strings in a static compression dictionary even though the dictionary is structured so that all children of the same parent have sequential index numbering. The children of a parent are in collating sequence order, and adjacent children that are nonadjacent in the collating sequence have a conceptual epsilon entry between them, which entry represents a match on the parent and a direction in the collating sequence. Code words for actual children are formed by using a dictionary entry index to locate a translation table entry containing a code word. Code words for epsilon entries are formed by using an entry index for an actual child to locate a translation table entry and then adding or subtracting one to or from the code word in the entry.

Abstract: In an analog/digital converting circuit, when an analog input voltage exceeds a reference voltage, the analog input voltage is modified into analog voltages not exceeding the reference voltage, and comparison voltages generated by dividing the reference voltage are compared with the modified analog voltages.

Abstract: A system for compressing digital data at one byte-per-cycle throughput by removing redundancy before storage or transmission. The system includes an improved Ziv-Lempel LZ1 process that uses a history buffer to save the most recent source string symbols for use in encoding the source symbols as "match-length" and "match-offset" tokens. The match-length code symbols are selected from two groups of buckets that are assigned variable-length prefixes for the shorter, more probable match-lengths and a fixed-length prefix code for the longer, less probable match-lengths. This exploits a transition from Laplacian match-length probability distribution to Uniform match-length probability distribution for longer match-lengths. The offset code field length is reduced during start-up to improve start-up compression efficiency during filling of the history buffer. The match-length code book is limited to a maximum value T<256 to limit latency and simplify the process.

Abstract: A signal-processing circuit has the first reference-voltage setting circuit for setting a lower-limit reference voltage and an upper-limit reference voltage for the first A/D converter, a data-storing section for storing digital data obtained by the first A/D converter, and the second reference-voltage setting circuit for setting a lower-limit reference voltage for the second A/D converter to a voltage that is lower than the voltage corresponding to the digital data stored in the data-storing section and that is higher than the lower-limit reference voltage set by the first reference-voltage setting circuit, as well as for setting an upper-limit reference voltage for the second A/D converter to a voltage that is higher than the voltage corresponding to the digital data stored in the data-storing section and that is lower than the upper-limit reference voltage set by the first reference-voltage setting circuit.

Abstract: A novel method and apparatus is disclosed for controlling inverse discrete cosine transform ("IDCT") mismatch between an encoder and decoder using different IDCT implementations under all coding conditions. Sychronization between the encoder and decoder is forced by selectively setting certain small DCT coefficients, which are prone to mismatch, to zero at the encoder. Advantageously, the invention may be implemented solely in the encoder to minimize system complexity and cost, and allow for IDCT mismatch control utilizing conventional decoders.

Abstract: The present invention is an apparatus and method for increasing the density of run-length-limited (RLL) block codes without increasing error propagation. By inserting a number of uncoded bytes (M) between each coded byte, the coding density is thereby increased. Starting with an RLL code with a block length (I) which is, for example, a multiple of 8, a number (M) of uncoded bytes may be inserted between each coded byte. The resulting density is: (I+8M)/(J+8M), wherein the resulting k constraint, of the (d,k,l) constraints is increased by 8M, and the resulting l constraint is increased by 4M. For example, starting with an RLL code having a coding density of 8/9 (I=8, J=9) and constraint set of (0,4,4), inserting one uncoded byte between each coded byte (M=1) results in a coding density of 16/17 which is 5.88% greater than the original 8/9 coding density. The constraint set is also increased to (0,12,8), where k is increased by 8 and l is increased by 4.

Abstract: A method and apparatus for an oversampled single bit digital to analog convertor (DAC) is accomplished by using an FIR filter as the analog reconstruction filter, wherein the FIR filter includes primary current sourcing circuitry and secondary current sourcing circuitry. The primary current sourcing circuitry is used to produce a portion of the FIR coefficients having relatively large values, while the secondary current sourcing circuitry is used to fine tune the FIR coefficients having the relatively large values and to produce the other FIR coefficients. Combining the results of the primary current sourcing circuitry and the secondary current sourcing circuitry produces an analog signal.

Abstract: A division technique unified quantizer-dequantizer circuit is disclosed. The unified quantizer-dequantizer includes a division circuit receiving a half step size q and an input signal x. The division circuit outputs a quantized coefficient signal y and a remainder R, where ##EQU1## The unified quantizer-dequantizer also includes a circuit receiving the quantized coefficient signal y, the remainder R, the half step size q and the input signal x.

Abstract: A distributed delta-sigma analog-to-digital (A/D) converter is partitioned between an ultrasonic probe and an imaging console which are coupled to each other by optical links. The ultrasonic probe houses an integrator for receiving an analog input signal and generating an integrated analog output signal. The integrated output signal is supplied to a light emitting diode for generating a light beam. The probe also houses photoconductive switches for coupling positive and negative reference voltages to a summing node of the integrator. The imaging console houses a photodiode for receiving the light beam via a fiber optic cable and converting the light beam to an analog electrical signal which is later converted to a digital signal. A feedback loop includes an internal A/D converter in the console that is coupled to the photoconductive switches via LED-generated light beams passed through other fiber optic cabling.