Patents Examined by Jason Lappas
  • Patent number: 12009028
    Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: June 11, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Graziano Mirichigni, Paolo Amato, Federico Pio, Alessandro Orlando, Marco Sforzin
  • Patent number: 12009033
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Patent number: 12002514
    Abstract: A nonvolatile memory may include; a first memory cell array including a first selection transistor connected to a first string selection line, a second memory cell array including a second selection transistor connected to a second string selection line and spaced apart from the first string selection line by a first cutting line, and a peripheral circuit. The peripheral circuit may provide a first program voltage to the first selection transistor, provide a second program voltage to the second selection transistor different from the first program voltage, program the first selection transistor with a first threshold voltage in response to the first program voltage, and program the second selection transistor with a second threshold voltage level greater than the first threshold voltage in response to the second program voltage.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: June 4, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Park, Won-Taeck Jung, Han-Jun Lee, Su Chang Jeon
  • Patent number: 12002540
    Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: June 4, 2024
    Assignee: RAMBUS INC.
    Inventors: Ian Shaeffer, Kyung Suk Oh
  • Patent number: 12002503
    Abstract: The present disclosure provides a memory circuit and a memory. The memory circuit at least includes a plurality of memory blocks. Each of the memory blocks includes a first memory sub-block, a second memory sub-block, and a third memory sub-block arranged in sequence; the second memory sub-block includes a first memory unit and a second memory unit; the first memory sub-block and the first memory unit are configured to store high-order bytes; the second memory unit and the third memory sub-block are configured to store low-order bytes; and in an arrangement direction of memory sub-blocks, different memory units that are arranged side by side have different block selection addresses.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: June 4, 2024
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Sungsoo Chi
  • Patent number: 11996147
    Abstract: A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.
    Type: Grant
    Filed: March 26, 2022
    Date of Patent: May 28, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Yen-Cheng Chiu
  • Patent number: 11996164
    Abstract: Within a memory control component, command/address circuitry transmits a first command/address value to a memory component during a first interval and a second command/address value to the memory component during a second interval, and timing circuitry transmits a data strobe to the memory component during the first interval and a data clock to the memory component during the second interval. The timing circuitry transitions the data strobe from a parked state to a toggling state during the first interval at a predetermined time relative to transmission of the first command/address value and toggles the data clock throughout the second interval regardless of time of transmission of the second command/address value. Data signaling circuitry transmits first write data to the memory component during the first interval synchronously with the write-data strobe signal and transmits second write data to the memory component during the second interval synchronously with the write-data clock signal.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: May 28, 2024
    Assignee: Rambus Inc.
    Inventor: Torsten Partsch
  • Patent number: 11990190
    Abstract: A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: May 21, 2024
    Assignee: Kioxia Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 11978515
    Abstract: A semiconductor memory device capable of reducing failure caused by a source side effect after a large number of W/E cycles is provided. A reading method of a NAND flash memory includes: dividing multiple word lines connected to each memory cell of a NAND string into a group 1 of word lines WL0 to WLi?1, a group 2 of word lines WLi to WLj, . . . , a group y of word lines WLj+1 to WLk?1, and a group x of word lines WLk to WLn, presetting a relationship that each readout voltage (Vread1, Vread2, . . . , Vready, and Vreadx) corresponding to each group increases toward a bit line side, and applying a readout voltage to a selected word line according to the relationship.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: May 7, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Riichiro Shirota, Masaru Yano
  • Patent number: 11980029
    Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 7, 2024
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Hsueh-Wei Chen
  • Patent number: 11972800
    Abstract: A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second floating gate transistor and a second select transistor. The first select transistor is connected with a program source line and a program word line. The first floating gate transistor includes a floating gate. The first floating gate transistor is connected with the first select transistor and a program bit line. The second floating gate transistor includes a floating gate. The second floating gate transistor is connected with a read source line. The second select transistor is connected with the second floating gate transistor, the read word line and the read bit line. The floating gate of the second floating gate transistor is connected with the floating gate of the first floating gate transistor.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: April 30, 2024
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Chun Chen, Chun-Hung Lin
  • Patent number: 11972805
    Abstract: In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the lower limit for erased non-volatile memory cells, and applying programming to non-volatile memory cells connected to the first set of bit lines while inhibiting programming for non-volatile memory cells connected to the second set of bit lines.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: April 30, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Yi Song, Yanjie Wang, Jiahui Yuan
  • Patent number: 11967394
    Abstract: Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods. To increase memory density, the memory array has a first memory sub-bank and one or more second memory sub-banks. The first memory sub-bank includes a first bit line(s) for each of its memory column circuits. To avoid the need to extend the length of the first bit lines to be coupled to the second memory bit cells in the second memory sub-bank, each memory sub-bank has its own dedicated first and second bit lines coupling their respective memory bit cells to access circuitry. The second bit lines effectively “fly” independent of the first bit lines of the first memory sub-bank. The first bit lines of the first memory sub-bank do not have to be extended in length to provide bit lines for the second memory sub-bank.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: April 23, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pramod Kolar, Robert A. Sweitzer
  • Patent number: 11967380
    Abstract: According to One embodiment, a semiconductor memory device includes: a first memory cell array; a second memory cell array arranged above the memory cell array; a third memory cell array arranged adjacent to the first memory cell array; a fourth memory cell array arranged above the third memory cell array and arranged adjacent to the second memory cell array; a first word line coupled to the first memory cell array and the second memory cell array; a second word line coupled to the third memory cell array and the fourth memory cell array; a first bit line coupled to the first memory cell array and the fourth memory cell array; and a second bit line coupled to the second memory cell array and the third memory cell array.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: April 23, 2024
    Assignee: Kioxia Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 11967382
    Abstract: The memory device includes a plurality of dies, and each die includes a plurality of blocks with a plurality of word lines. Some of the word lines are arranged in a plurality of exclusive OR (XOR) sets with each XOR set containing word lines in the same positions across the plurality of dies. The memory device further includes a controller that is configured to program the word lines of the blocks of at least one of the dies in a first programming direction. The controller is further configured to program the word lines of the blocks of at least one other die in a second programming direction that is opposite of the first programming direction.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: April 23, 2024
    Assignee: SanDisk Technologies, LLC
    Inventors: Qing Li, Henry Chin, Xiaoyu Yang
  • Patent number: 11963343
    Abstract: A semiconductor device capable of obtaining the threshold voltage of a transistor is provided. The semiconductor device includes a first transistor, a first capacitor, a first output terminal, a first switch, and a second switch. A gate and a source of the first transistor are electrically connected to each other. A first terminal of the first capacitor is electrically connected to the source. A second terminal and the first output terminal of the first capacitor are electrically connected to a back gate of the first transistor. The first switch controls input of a first voltage to the back gate. A second voltage is input to a drain of the first transistor. The second switch controls input of a third voltage to the source.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hitoshi Kunitake, Ryunosuke Honda, Tomoaki Atsumi
  • Patent number: 11955179
    Abstract: The semiconductor memory device of the embodiment includes: a substrate; a first memory pillar extending in a first direction from the substrate, the first memory pillar including first memory cell transistors, a first selection transistor, a second selection transistor, second memory cell transistors, a third selection transistor, a fourth selection transistor, third memory cell transistors, a fifth selection transistor, a sixth selection transistor, fourth memory cell transistors, a seventh selection transistor, and an eighth selection transistor; a first select gate line; first word lines; a second select gate line; a third select gate line; second word lines; a fourth select gate line; a fifth select gate line; third word lines; a sixth select gate line; a seventh select gate line; fourth word lines; and an eighth select gate line.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: April 9, 2024
    Assignee: Kioxia Corporation
    Inventor: Yuki Inuzuka
  • Patent number: 11955158
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: April 9, 2024
    Inventors: Jason M. Brown, Daniel B. Penney
  • Patent number: 11948643
    Abstract: A nonvolatile memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory regions coupled to a plurality of word lines. The plurality of memory regions include first and second memory regions coupled to upper and lower word lines, respectively. The control logic performs, after receiving first data and second data, a first program operation on the first memory region to store the first data and a second program operation on the second memory region to store the second data.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Seunggu Ji, Yong Il Jung
  • Patent number: 11942162
    Abstract: A method for operating a memory device is provided. The method includes providing a high voltage signal to a memory cell array including a plurality of memory cells using a first wiring, providing a logic signal to the memory cell array using a second wiring, and providing a shielding signal to the memory cell array using a third wiring arranged between the first wiring and the second wiring. A highest voltage level of the logic signal is lower than a highest voltage level of the high voltage signal, and the shielding signal includes a negative first voltage level in a first mode and a positive second voltage level in a second mode.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: March 26, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung Soo Kim, Dae Han Kim, Jong Min Kim, Myoung Won Yoon