Patents Examined by Jason Lappas
  • Patent number: 11120877
    Abstract: A program method capable of reducing a peak current of a program operation is provided. The program method of a flash memory includes following steps: charging selective bit lines and non-selective bit lines by using a virtual voltage with weak driving ability during the time from t0 to t1 and a virtual voltage with strong driving ability during the time from t1 to t2, switching at least the non-selective bit lines to use the virtual voltage with weak driving ability for charging during at least the time from t2 to t3 when starting to discharge the selective bit lines connected to selective storage cells to a GND voltage level at time t2, and then applying program voltages to selective word lines.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: September 14, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Sho Okabe
  • Patent number: 11114147
    Abstract: Methods, systems, and devices for operating a memory cell or cells are described. A capacitor coupled with an access line may be precharged and then boosted such that the charge stored in the capacitor is elevated to a higher voltage with respect to a memory cell. The boosted charge in the capacitor may support sensing operations that would otherwise require a relatively higher voltage. Some embodiments may employ charge amplification between an access line and a sense component, which may amplify signals between the memory cell and the sense component, and reduce charge sharing between these components. Some embodiments may employ “sample-and-hold” operations, which may re-use certain components of a sense component to separately generate a signal and a reference, reducing sensitivity to manufacturing and/or operational tolerances. In some embodiments, sensing may be further improved by employing “self-reference” operations that use a memory cell to generate its own reference.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ferdinando Bedeschi, Umberto Di Vincenzo
  • Patent number: 11107534
    Abstract: A memory device includes a memory array. The memory array has a plurality of memory cells arranged in rows and columns. The gates of the memory cells in the same row are coupled to each other and connected to a word line. The drains of the memory cells in the same column are coupled to each other and connected to a bit line. The sources of the memory cells in the same row are coupled to each other, and the sources of the memory cells in the two adjacent rows are connected to different respective source lines.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 31, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Wen-Chiao Ho
  • Patent number: 11107538
    Abstract: The present disclosure relates to an electronic device. A storage device includes a memory device configured to include a plurality of memory cells and a memory controller configured to determine a read voltage for a read operation to be performed on the memory device according to whether the read operation is a cache read operation.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Ho Her, Dong Hyun Kim, Seung Il Kim, Yong Ho Kim, Jae Min Lee, Seon Young Choi
  • Patent number: 11107859
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a magnetic tunnel junction (MTJ) device disposed within a dielectric structure over a substrate. The MTJ device has a MTJ disposed between a first electrode and a second electrode. A first unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The first unipolar selector is configured to allow current to flow through the MTJ device along a first direction. A second unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The second unipolar selector is configured to allow current to flow through the MTJ device along a second direction opposite the first direction.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Katherine H. Chiang, Chung-Te Lin, Mauricio Manfrini
  • Patent number: 11101012
    Abstract: A magnetic storage device includes a magnetic body including first and second magnetic regions and a magnetic connection region that connects the first and second magnetic regions, and in which a plurality of magnetic domains each storing information by a magnetization direction thereof is formed, a read element that is electrically connected to the magnetic connection region and by which a magnetization direction of one of the magnetic domains is read, and a write element by which a magnetic domain having a magnetization direction is formed in the magnetic body according to information to be stored. The magnetic domains formed in each of the first and second magnetic regions are shifted in a predetermined direction in response to current that flows through the corresponding one of the first and second magnetic regions.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 24, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshihiro Ueda, Shinji Miyano
  • Patent number: 11094380
    Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: August 17, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Naoya Tokiwa
  • Patent number: 11087836
    Abstract: Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 10, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Bernardo Rub, Mostafa El Gamal
  • Patent number: 11081162
    Abstract: This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a NAND string channel is biased by biasing the source line coupled to the NAND string by the plurality of source-side select gates. Finally, the plurality of source-side select gates and the plurality of source side dummy word line select gates are discharged such that the channel maintains an electrical path to the source line.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: August 3, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Sarath Puthenthermadam, Yu-Chung Lien, Huai-Yuan Tseng
  • Patent number: 11062741
    Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Jun Yoon, Hyun Seung Kim
  • Patent number: 11055011
    Abstract: A storage device includes a first nonvolatile memory device, a second nonvolatile memory device, and a data line. The second nonvolatile memory device is of a different type from the first nonvolatile memory device. The data line is shared by the first nonvolatile memory device and the second nonvolatile memory device. First data is simultaneously provided to the first nonvolatile memory device and the second nonvolatile memory device through the data line, the first data is written to the second nonvolatile memory device, and the first data is reprogrammed into the first nonvolatile memory device by reading the first data from the second nonvolatile memory device and providing the read first data to the first nonvolatile memory device.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee Sung Kim, Hyun Wook Shin
  • Patent number: 11056183
    Abstract: Various implementations described herein are directed to an integrated circuit having multiple bitcell arrays and multiple input ports including a single write input port for the multiple bitcell arrays and multiple read input ports for the multiple bitcell arrays. The integrated circuit may include multiple read output ports for the multiple bitcell arrays. The single write input port is used for writing data to the multiple bitcell arrays, and the multiple read input ports are used separately for reading data from the multiple bitcell arrays for output to the multiple read output ports.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 6, 2021
    Assignee: Arm Limited
    Inventors: Yew Keong Chong, Andy Wangkun Chen, Sriram Thyagarajan
  • Patent number: 11056179
    Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Chong J. Zhao, James A. McCall, Shigeki Tomishima, George Vergis, Kuljit S. Bains
  • Patent number: 11049530
    Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Jun Yoon, Hyun Seung Kim
  • Patent number: 11048441
    Abstract: A semiconductor device includes an internal clock generation circuit, a command generation circuit, and an address generation circuit. The internal clock generation circuit generates a command clock signal and an inverted command clock signal, wherein a cycle of the command clock signal and a cycle of the inverted command clock signal are determined by a mode. The command generation circuit generates a first command based on a first internal control signal and the command clock signal and generates a second command based on a second internal control signal and the inverted command clock signal. The address generation circuit generates a latch address based on the first internal control signal or a second internal control signal.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Woo Jin Kang, Seung Wook Oh
  • Patent number: 11048431
    Abstract: Disclosed is a flip-flop based on a nonvolatile memory. The flip-flop based on the nonvolatile memory includes a flip-flop unit to output output data, a nonvolatile memory unit electrically connected to the flip-flop unit and to store backup data, and a backup controller to selectively control a backup operation for backing up the output data to the backup data, based on whether the backup data are the same as the output data.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: June 29, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Jongsun Park, Gyuseong Kang
  • Patent number: 11048443
    Abstract: A circuit comprising a non-volatile memory array, an Input/Output (IO) circuit, a decoder circuit, a control circuit, and a read/write circuit. The non-volatile memory array couples to an address decoder that identifies a location within the non-volatile memory array for a storage command. The IO circuit couples to a decoder circuit through a control bus. The decoder circuit decodes a command address and storage command from a fixed length command sequence received by the IO circuit over the data bus. The decoder circuit may include a serial-in parallel out (SIPO) circuit for decoding and parallel operation. The control circuit couples to the IO and decoder circuits and generates control signals to execute decoded storage commands. The read/write circuit couples to the non-volatile memory array and the control circuit. The read/write circuit transfers data between the non-volatile memory array and the IO circuit in response to the storage commands.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: June 29, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Sajal Mittal, Sneha Bhatia, Vinayak Ghatawade
  • Patent number: 11037617
    Abstract: A method of operating a memory device is provided, comprising determining a number of operations corresponding to a memory location during a first timing period; and scheduling an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold. A memory device is provided, comprising a memory including a memory location; and circuitry configured to: determine a number of operations corresponding to the memory location during a first timing period; and schedule an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 11031084
    Abstract: A memory device, in accordance with a method of operation, may include: a plurality of pages coupled to a common word line and configured to be sequentially selected by different select lines; a program operation controller configured to perform a program operation on a first page that is to be programmed first, among the plurality of pages; and a start loop manager configured to generate start loop information about a program loop in which program verification corresponding to each of a plurality of program states to be formed by threshold voltages of memory cells included in the first page starts, during the program operation on the first page. The program operation controller is further configured to perform a program operation on a second page to be programmed subsequent to the first page, among the plurality of pages, based on the start loop information.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventors: Jong Hoon Lee, Se Chun Park
  • Patent number: 11031085
    Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: June 8, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Mohan V Dunga, Pitamber Shukla