Abstract: A lighting device may include a light source, a control circuit, and a communication device positioned in communication with the control circuit. The communication device may be configured to receive a transmission from a user device, and the transmission may include a data structure. The data structure may include a show packet and an event packet. The show packet may include an ID string and information regarding a number of event packets associated with the data structure, and the event packet may include information regarding a lighting spectrum, a fade type, a fade duration, and a hold duration. The control circuit may be configured to operate the light source to emit light transitioning from a present light emission having a present spectral power distribution to a light emission having spectral power distribution indicated by the lighting spectrum according to the fade type and fade duration.

Abstract: An AC direct drive lamp including a leakage current protection circuit includes an input stage configured to receive external power, a rectification circuit configured to rectify the external power received from the input stage, a control module electrically connected to the output stage of the rectification circuit and configured to sense and control the state of at least one of the rectification circuit, a switch module, and a light source, the switch module connected between the input stage and the control module in a feedback form and configured to switch on/off depending on a predetermined condition, and the light source electrically connected to the control module and configured to radiate light when power is applied.

Abstract: The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and the branch includes a tunable delay buffer that operates to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.

Abstract: Systems and methods for improving color accuracy and uniformity in LED illumination systems are disclosed including light engines and switching circuits for controlling the addition or subtraction of light from one or more color light sources of the light engines to produce light of a uniform and consistent color. Systems and methods of providing LED light engines and associated illumination spectrums that are both visually appealing and rich in melanopic flux are also disclosed.

Abstract: A system, comprising a dual voltage supply configured to receive a logic state input voltage and configured to output an output voltage, wherein the dual voltage supply is configured to output a nominal voltage at a high state of the logic state input voltage and the dual voltage supply is configured to output a high voltage at a low state of the logic state input voltage, a pre-charge capacitor is configured to receive the output voltage of the dual voltage supply and an output buffer has an output buffer power input is coupled to the pre-charge capacitor and configured to receive the output voltage of the dual voltage supply, an output buffer signal input is configured to receive the logic state input voltage and an output buffer output is configured to output a digital output signal.

Abstract: An LED driver circuit and a method prevent LED turn-off flash when input power is lost to the driver circuit. The driver circuit includes a DC-DC converter that provides an LED drive voltage to an LED load. A voltage drop sensing circuit detects the loss of input power and discharges a filter capacitor that provides operating power to a controller in a DC-DC converter. The controller turns off to halt the operation of the DC-DC converter before the voltage provided to the LED load decreases to a turn-off threshold of the LED load. The DC-DC converter cannot recharge a load capacitor across the LED load. Thus, once the LEDs in the LED load turn off, the LEDs remain off until the input power is restored.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

Abstract: Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

Abstract: A system in a package (SIP) has a first die with a first internal voltage level, first die-to-die output circuitry, first die-to-die input circuitry, and first internal logic and a second die with a second internal voltage level, second die-to-die output circuitry, second die-to-die input circuitry, and second internal logic. A first signal is provided to the second internal logic via the first die-to-die output circuitry and the second die-to-die input circuitry, wherein each of the first die-to-die output circuitry and second die-to-die input circuitry selectively level shift the first signal based on the first and second internal voltage levels. A second signal is provided to the first internal logic via the second die-to-die output circuitry and the first die-to-die input circuitry, wherein each of the second die-to-die output circuitry and first die-to-die input circuitry selectively level shift the second signal based on the first and second internal voltage levels.

Abstract: Resistance elements, including Magnetic Tunnel Junction devices are configured as magnetoelectronic (ME) devices. These resistive devices are useable as circuit building blocks in reconfigurable processing systems, including as logic circuits, non-volatile switches and memory cells.

Abstract: An integrated circuit includes a field programmable gate array including: (i) a plurality of memory cells (e.g., static memory cells) to store data, wherein each memory cell includes a first output, (ii) a multiplexer including inputs, an output and input selects, (iii) a plurality of poly-silicon conductors, each poly-silicon conductor is disposed in the substrate and connected to the first output of an associated memory cell, (iv) poly-silicon extensions, each poly-silicon extension is (a) connected to an associated poly-silicon conductor and (b) coupled to an associated input select of the multiplexer, wherein the poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor in the field programmable gate array.

Abstract: A semiconductor device may include a ZQ calibration circuit, a reference code setting circuit, a variable information generating circuit, and an internal circuit. The ZQ calibration circuit may perform a ZQ calibration operation in response to a ZQ calibration enable signal to generate a ZQ calibration code. The reference code generating circuit may output a predetermined code value as a reference code. The variable information generating circuit may compare the ZQ calibration code to the reference code to generate variable information. The internal circuit may determine operation timings based on a difference between the ZQ calibration code and the reference code.

Abstract: A programming system includes an upper computer, a calculation module, and a first signal conversion module. The calculation module includes a second signal conversion module and a programming interface. The upper computer is configured to convert programming data into first bus signals. When the calculation module is in a normal programming state, the second signal conversion module converts the first bus signals into first clock signals and first data signals to program the calculation module. When the calculation module is in a non-normal programming state, the first signal conversion module converts the first bus signals into second clock signals and second data signals to program the calculation module. A programming method is also provided.

Abstract: A cooperative adaptive lighting system for motor vehicles in which a vehicle transmits its geographic coordinates and receives similar coordinates from other vehicles, pedestrians, and stationary warning devices. Using the coordinates, the vehicle computes distances, and relative position more specifically, to those entities. When the distances become sufficiently small, indicating that the entities fall within headlight range, the vehicle alters its headlight beams to either (1) throw more light on an entity, (2) reduce light reaching the entity as appropriate, or (3) change a lighting pattern as appropriate.

Abstract: Hybrid Hall Effect Devices implemented with Spin Transfer Torque write capability are configured as magnetoelectronic (ME) devices. These devices are useable as circuit building blocks in reconfigurable processing systems, including as logic circuits, non-volatile switches and memory cells.

Abstract: A device includes a multiplexer circuit with a plurality of input circuits. Each input circuit is connected to a respective input node and a shared output node. The input circuits are configured to pass, in response to a respective control signal, a signal between the respective input and shared output node. An output circuit is configured to store data from the shared output node in a latch mode and to act as a buffer in a pass-through mode. A control circuit is configured to switch, in response to a configuration signal, the output circuit between the latch mode and the pass-through mode.

Abstract: Systems and methods are described herein for coupling electromagnetic (EM) energy from a remotely-located primary antenna into a plasma ion source. The EM energy is radiated by a first by through an intermediary secondary antenna. The embodiments described herein enable the elevation of the plasma ion source to a high electric potential bias relative to the primary antenna, which can be maintained at or near a grounded electric potential.

Abstract: A ripple reduction circuit is provided. The ripple reduction circuit may include a ripple capacitor configured to drive at least a first segment of a string of light emitting diodes (LEDs), a first diode having an anode coupled to the ripple capacitor, and a cathode configured to be coupled to an input end of the first LED segment, a second diode having a cathode coupled to the ripple capacitor and the anode of the first diode, and an anode configured to be coupled between the first LED segment and a second LED segment of the string of LEDs, a third diode having an anode coupled to the ripple capacitor, and a cathode configured to be coupled to a last LED segment of the string of LEDs, and a fourth diode having a cathode coupled to the ripple capacitor and the anode of the third diode.

Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.

Abstract: An electronic device 2 has circuitry 4 which operates in a first voltage domain 6 supplied with a first voltage level VDD1 and a reference voltage level. A voltage regulator 14 generates the first voltage level VDD1 from a second voltage level VDD2 higher than the first voltage level VDD1. At least one power gate 20, 30 is provided for selectively coupling the circuitry 4 to one of the first voltage level VDD1 or the reference level. The control signal 22 for the power gate 20, 30 is generated in a second voltage domain supplied with a higher voltage level VDD2 or VDD3 derived from the second voltage level VDD2 supplied to the voltage regulator 14. Hence, an existing high voltage source within the device 2 can be reused for applying a boosted voltage to power gates to improve efficiency of power gating.