Abstract: A method for providing built-in self test (BiST) for an analog-to-digital converter (ADC) by automatic test equipment (ATE) is described. Output codes are received from the ADC. The output codes are translated to generate a functional pattern. Performance metrics are determined for the ADC using the functional pattern. The ADC may be on a device-under-test (DUT).

Abstract: A communication service equipment and a search and rescue terminal device for vessels that are set on board to provide radio communication service including at least one radio signal transmission and reception units, a modulation and demodulation unit, a location information receiving unit, a plurality of frequency conversion unit, signal processing units each connected to the frequency conversion unit, a main control unit, and control the signal processing unit.

Abstract: A wireless communication circuit has a second control circuit which reduces the gain of the differential converter when the signal level of the RF signal is at least a specified level and the RF signal includes a disturbing wave of a predetermined level or higher.

Abstract: A receiver has a pre-stage variable gain amplifier configured to amplify an RF signal received by an antenna, a frequency converter configured to convert an output signal of the pre-stage variable gain amplifier into a low frequency signal to output the low frequency signal, a filter unit configured to selectively extract a receiving channel frequency band component from the low frequency signal, a post-stage variable gain amplifier configured to amplify the output signal of the filter unit, a pre-stage amplifier controller configured to adjust a gain of the pre-stage variable gain amplifier so that an output amplitude of the frequency converter approaches a target value, a post-stage amplifier controller configured to adjust a gain of the post-stage variable gain amplifier so that an output amplitude of the post-stage variable gain amplifier approaches a target value, and an adaptive controller configured to detect a receiving status based on the gain of the pre-stage variable gain amplifier and the gain of

Abstract: One embodiment of the present invention includes an analog-to-digital converter (ADC) system. The system includes an ADC configured to generate digital samples that are digital versions of at least one analog signal at a sampling frequency and a memory configured to store data corresponding to an average value of the digital samples in at least one register. The system further includes a processor configured to access the data corresponding to the average value for processing at an access frequency that is less than the sampling frequency.

Abstract: A comparison circuit includes: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.

Abstract: A generation method of an analogue signal generated by a PWM signal whose cyclic ratio and period are parametrizable is discussed. It is thus possible choose the pair formed from the cyclic ratio and the period producing an analogue value that is the closest to the value corresponding to the programmed command value. But the differences between the analogue values can be very great and generate zones of imprecision of variable width. Outside of these zones, the generated analogue signal is very precise. Therefore, when the command value associated with a pair is imprecise, a digital shift is applied to the command value at the same time as the application of an analogue shift means. Both shifts have the same amplitude and of opposite directions such that the cancel each other out, producing a precise analogue value. A device for generating an analogue signal implementing the method is also discussed.

Abstract: A deflate decompressor includes at least one decompressor unit, a memory access controller, a feedback path, and an output buffer unit. The memory access controller is coupled to the decompressor unit via a data path and includes a data buffer to receive the data stream and temporarily buffer a first portion the data stream. The memory access controller transfers fixed length data units of the data stream from the data buffer to the decompressor unit with reference to a memory pointer pointing into the memory buffer. The feedback path couples the decompressor unit to the memory access controller to feed back decrement values to the memory access controller for updating the memory pointer. The decrement values each indicate a number of bits unused by the decompressor unit when decoding the fixed length data units. The output buffer unit buffers a second portion of the data stream after decompression.

Abstract: A semi-automatically sliding mobile terminal includes a first main body, a second main body, a hinge unit, and a guide line. The second main body slides on the upper side of the first main body. The hinge unit includes a coupler coupled to the first main body and a spring unit compressing and expanding in a lateral direction. The guide unit includes a curved line having an ascending curved line, a crest, and a descending curved line that are formed in a longitudinal direction. When the second main body moves, the spring unit compresses or expands along the guide line. The spring unit compresses before passing over the crest and expands after passing over the crest. After the crest, the second main body moves semi-automatically due to elastic force of the spring unit.

Abstract: A method for encoding an input file into an output file that is compressed so that the number of bits required to represent the output file is less than the number of bits of the input file. The encoding method includes the parsing of the input file into a series of data items, the data items having an order and collectively corresponding to the input file. The encoding method compares the series of data items against a static dictionary having at least mappings between terminal sequence pointers and representations of data items.

Abstract: A wireless apparatus which can realize a DFS function that avoidance of interference with radar is considered in an Ad-Hoc mode under a multihop circumstance is provided. A Beacon frame is transmitted at a shorter interval than a previously set interval when radar is detected by wireless apparatuses N1 to N6 which have a DFS function which perform avoidance of interference with radar.

Abstract: A capacitor array includes a plurality of capacitor components each having a first node and a second node, and first nodes of the capacitor components are coupled to each other. A calibration method for the capacitor array utilizes a calibration capacitor component to couple the first nodes. Then, the calibration method determines a capacitance indication value regarding the specific capacitor component by coupling different references voltage to a second node of the specific capacitor component and coupling different test voltages to a second node of the calibration capacitor component. Accordingly, the calibration method calibrates the capacitance mismatches of the capacitor array in the digital domain.

Abstract: Systems and methods for digital upconversion of digital signals are provided. In one embodiment, the system includes a digital frequency adjustment system and a digital to analog conversion system. In a feature of the embodiment, the digital frequency adjustment system consists of set of digital upconversion and upsample elements that shift upwards the frequency of baseband signals. In a further feature of the embodiment, a tree structure of sets of upsample and upconversion elements is used. In another embodiment, the system includes digital and analog frequency adjustment systems in which the frequencies of the input signals are partially upshifted within both the digital and analog domains. Methods for digital upconversion of digital signals are also provided.

Abstract: An inter-stage gain of a conversion stage of a pipeline ADC is calibrated by imposing a perturbation to a sub-ADC within the conversion stage and adjusting a gain factor in a closed loop manner so as to make a conversion output substantially independent of the perturbation.

Abstract: A parallel to serial conversion circuit makes output data normally swing even in a high-speed operation. The parallel to serial conversion circuit includes a main selection block configured to drive an output node sequentially in response to data on a first line and data on a second line, and a subsequent selection block configured to drive the output node sequentially in response to data on a subsequent first line and data on a subsequent second line, wherein the output node is driven by inverted data of the data on the subsequent first line and inverted data of the data on the subsequent second line.

Abstract: In the digital calibration technique of the conventional time-interleaved analog/digital converter, it is impossible to perform highly-accurate calibration that supports a high-speed sampling rate of the next-generation application and achieves a high resolution. For its solution, a reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit.

Abstract: In a compression/decompression apparatus that compresses or decompresses a plurality of sub-block data elements, a compressing unit compresses the plurality of sub-block data elements in parallel by a plurality of compressors. A combining unit combines compressed data by the plurality of compressors to generate a transfer data such that the transfer data has a transfer data amount corresponding to a plurality of transferring cycles, each transfer data amount per one transferring cycle is divided into a plurality of segmented regions in same number as number of the sub-block data elements, and allocating each compressed data of the plurality of sub-block data elements is allocated to a corresponding segmented region of the plurality of segmented regions, and outputs the transfer data to the external memory. A decompressing unit decompresses the transfer data read from the external memory in parallel by using a plurality of decompressors. An arranging unit performs address conversion.

Abstract: A device that includes an internal data storage location coupled to an electrical conductor and an analog-to-digital converter coupled to the internal data storage location via the electrical conductor. In some embodiments, the analog-to-digital converter includes a comparator having an input coupled to the electrical conductor and a switch coupled to the electrical conductor.

Abstract: An A/D conversion circuit includes: a sample-and-hold circuit adapted to sample and hold an input signal to output a sampled signal; a control circuit adapted to output successive approximation data; a first D/A conversion circuit adapted to perform D/A conversion on the successive approximation data to output a first D/A output signal; a second D/A conversion circuit adapted to perform D/A conversion on time-varying code data to output a second D/A output signal; and a comparison circuit adapted to perform a process of comparing the first D/A output signal, and an addition signal of the sampled signal and the second D/A output signal, and to output a comparison result signal, wherein the control circuit has a successive approximation register to which register values are set in accordance with the comparison result signal, outputs successive approximation result data after all of the register values of the successive approximation register have been determined, and subtracts the code data from the successive

Abstract: A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.