Abstract: The analog-digital converter (ADC) includes a modulator and a digital integrator. The modulator is configured to modulate an input signal and output a modulated signal. The digital integrator includes a plurality of accumulators serially connected to one another. The digital integrator is configured to integrate the modulated signal to output an integration result.

Abstract: A transmitter device comprises a digital part and an analog part. The digital part comprises a digital modulator for receiving bits and for digitally modulating the received bits. The transmitter device includes first and second digital-to-analog converters. The transmitter device furthermore comprises at least one filter unit arranged in the digital part and coupled between at least one of the first and second digital-to-analog converters and the digital modulator. A table unit is coupled to the at least one filter unit and is used to store pre-defined compensation filter values for the at least one filter unit to compensate different delay mismatches in the analog part of the transmitter device. The filter values of the at least one filter unit are set to those compensation filter values as stored in the table unit (TU) which correspond to a determined delay mismatch.

Abstract: An analog to digital converting device is proposed for generating a digital output signal of an RF analog input signal. The device comprises a first analog to digital converter stage, a mixer, a second analog to digital converter stage and a digital filter. The first analog to digital converter stage generates a first and a second output signal. The first output signal is inputted in the filtering means. The second output signal is being down-converted to a signal with an intermediate frequency or DC. Thereafter, this down-converted signal is being fed to the second analog to digital converter stage. The digital output signal of this second stage is further processed together with the first digital output signal in the digital filter to a digital signal representative of the analog input signal.

Abstract: A method and system of providing a low battery charge warning in an electronic device that employs a rechargeable power source such as a rechargeable battery. The method and system determine whether a charge state of a battery is sufficient to provide the device with power for a predicted usage. The predicted usage and predicted power requirement may be determined from a usage profile of the device. The predicted usage and power requirement may also be determined from data associated with an event record as may be stored in a calendar application on the device. The method and system may provide an advance notice to the user of the device of a potential low battery situation.

Abstract: A folding analog-to-digital converter (ADC) is disclosed. The folding ADC includes a reference voltage generating unit generating a plurality of reference voltages, a low power analog pre-processing unit including a plurality of folders, each of which compares a voltage level of an analog input signal with a corresponding reference voltage of the plurality of reference voltages to generate a pair of differential folded outputs, a comparison unit that compares outputs of the low power analog pre-processing unit to output a digital signal, and an encoding unit that converts an output of the comparison unit into a binary code signal.

Abstract: A D/A conversion circuit in accordance with the present invention, which is provided with a switch swD, allows a writing operation of a voltage (a true gradation voltage) to be performed at a higher speed by first applying a first voltage (a voltage close to the true gradation voltage), which is supplied without passing through a resistor element, to an output line and then applying a second voltage (the true gradation voltage), which is supplied via the resistor element, to the output line. Thus, the present invention can provide a D/A conversion circuit capable of writing display data to liquid crystal cells with higher precision at higher speed, and a semiconductor device utilizing such a D/A conversion circuit.

Abstract: A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds.

Abstract: Various implementations relating to analog-to-digital converters are provided. A comparator of such a circuit is used for converting different analog input signals, while analog-to-digital conversion circuitry for these conversions is implemented at least partially separately. In other implementations, a comparator is used both for analog-to-digital conversion and for comparing an input signal to a constant or non-constant value.

Abstract: In one embodiment, the modulator in an analog-to-digital converter includes a first reset switch and second reset switch, each controlled by a reset signal. The first reset switch is connected in a first reset feedback path between an input and an output of an integrator stage, and the second reset switch connected in a second reset feedback path between the input and the output of the integrator stage.

Abstract: An apparatus is provided which has a first analog input and a second analog input. In a particular implementation, the first analog input is coupled to a first controllable oscillator and the second analog input is coupled to a second controllable oscillator. First and second digital output signals generated based on output oscillations from the first controllable oscillator and the second controllable oscillator are combined.

Abstract: According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.

Abstract: One embodiment of the present invention is a text acquisition system that includes: (a) a character stream application module; (b) a parallel property bit stream module; (c) an analysis module; (c) a character stream generator; and (d) a database.

Abstract: Hardware not currently being used is re-oriented to a new purpose. Sensors on a personal communication device monitor the environment around the device. Based on an analysis of that monitoring, an appropriate visual message is shown on an outside display screen of the device. The visual message is targeted toward those around the device rather than to the device's user. In some embodiments, the monitoring devices include a camera and a microphone. Images taken by the camera are analyzed in an attempt to detect persons or objects around the user or to determine where the user is located. Captured speech is analyzed to determine topics of conversation. The results of these analyses are fed into a decision-making process that determines what visual messages would be appropriate. In one embodiment, the visual message is an advertisement.

Abstract: A method and apparatus of a digital signal processor for coding of a significant map. The method for coding of a significant map includes carrying out a scan of at least a portion of a block of transform coefficients; calculating runs of zeros of the scanned data; and coding runs of zeros with variable length coding.

Abstract: A method of tuning an antenna circuit includes: (a) receiving a signal on an antenna, (b) producing a received signal strength indication based on the received signal, (c) using the received signal strength indication to produce a control voltage, (d) using the control voltage to control a capacitance in an antenna matching circuit, (e) changing the control voltage to minimize a ratio of a change in the received signal strength indication to a change in the control voltage and (f) repeating steps (a), (b), (c), (d) and (e). An apparatus that implements the method is also provided.

Abstract: There is provided a correction circuit for a D/A converter, comprising: a constant current source to be connected between high- and low-potential power source lines for supplying a power source voltage to the D/A converter; and a current controller which is adapted to control a current flowing to the constant current source in accordance with an input digital signal to the D/A converter, so as to reduce a variation of a sum of currents which, when the input digital signal to the D/A converter is changed, flows to the low-potential power source line from the high-potential power source line through the D/A converter and the constant current source, respectively.

Abstract: A voltage regulator uses a digital feedback technique to regulate the voltage at an output of the regulator. The voltage level of an output signal is measured. The voltage level of the output signal is compared to a first reference voltage. A programmable digital control logic block regulates the voltage level of the output signal and operates in a first mode if the voltage level of the output signal is above a first reference voltage and in a second mode if the voltage level of the output signal is below the first reference voltage. Depending on the mode of operation, the programmable digital control logic block provides digital control signals to other elements of the feedback loop.

Abstract: Various embodiments are disclosed relating to techniques of filtering and down-converting a received signal. In accordance with an example embodiment of the present invention, an analog signal may be received and amplified in a transconductance amplifier. The amplified signal may be connected to a switching arrangement and an impedance circuit connected in series, and frequency down-converted in a second circuit. The resulting analog base band signal may be fed back to a base band input between the switching arrangement and the impedance circuit.

Abstract: A RF circuit includes a master PCB, a plurality of slave PCBs and a plurality of antennas. The master PCB includes at least two RF ICs and at least two transceiving diplexer groups for tranceiving different frequency bands. Each transceiving diplexer group includes a plurality of transceiving diplexers transceiving a same frequency band and electrically connected to the RF ICs via PCB tracks without intersection. Each slave PCB includes a frequency division diplexer electrically connected to at least two transceiving diplexers respectively belonging to different tranceiving diplexer groups for respectively transmitting different frequency bands. Each antenna electrically connects to one of the division diplexers.

Abstract: A data compression apparatus and method for improving data compression efficiency are provided. The data compression apparatus includes a searcher for calculating costs, by searching domain blocks arranged in forward direction in a search range, between a range block and the domain blocks and for generating distance and difference information, by searching the costs in backward direction, between the range block and the domain block that incurs the lowest cost and a coder for encoding the distance and difference information into compressed data of the range block.