Abstract: A method and apparatus for an amplifier, such as a radio frequency amplifier embodied as an integrated circuit is disclosed. Embodiments provide for a wide range of operating powers with good energy efficiency at many power levels. Resonant components act to provide consistent operating parameters over the wide range of power levels used. The invention may operate in the microwave region or at other RFs.

Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output.

Abstract: A method and system for evolving electronic circuits based on defined rules. A first approach uses a network of nodes having established topological and behavioral relationships amongst themselves. An A/D converter is developed using this approach. A second approach employs software agents to create signal filters. The software agents are allowed to evolve in signal parameter space so as to match a reference signal, subject to established evolutionary rules and parameter space constraints. Narrowband and a low-pass filters can be formed using such agents.

Abstract: A latch architecture for driving unit current cell of a current-steering digital-to-analog converter (DAC) which reduces the drain-source voltage variation of the output current-source transistors and reduces the coupling of unwanted injection of input digital signals as well as clock signals is presented herein. Moreover, this latch helps to achieve lower glitch during code transition with improved dynamic performance. The latch effectively uses the intrinsic RC delay of most transistors within the latch architecture in order to achieve optimal crossing points of complementary control signals. Unwanted input injection or cross-talk is reduced by introducing transistors (904, 906, 932 and 934) that are off during code transitions without compromising the DAC update speed. Conflicts between currently held and new inputs are avoided in an effort to reduce the harmonic distortion.

Abstract: Method and apparatus for subclocking a SAR analog-to-digital converter. A method is disclosed for clocking the operation of a SAR analog-to-digital converter (ADC). A low frequency clock and a high frequency clock are provided. An analog input voltage is then tracked during a tracking phase to sample the value thereof. A conversion cycle referenced to an edge of the low frequency clock is then initiated. The sampled data is then converted in a conversion operation during a data conversion cycle, which conversion operation requires a plurality of conversion clock cycles, the timing of at least a portion of the conversion operation is controlled during the data conversion cycle utilizing the high frequency clock as the conversion clock.

Abstract: A low-distortion band-pass delta-sigma analog-to-digital converter (ADC), including an odd-phase sample and hold circuit coupled to a even-phase resonator, improves tolerance to mismatches between analog circuit components. The low-distortion ADC includes a feed-forward signal path that reduces, or eliminates, the input signal beyond the first summation point. In this way, the dynamic range and matching accuracy required of the resonator is reduced. An odd-phase sample and hold circuit shifts S/H spurious signals out-of-band. A two-phase resonator reduces in-band noise degradation caused by any mismatches between the resonator components.

Abstract: An attenuator includes a substrate having first and second surfaces and a plurality of discrete circuit elements. The first surface includes a first electrically conductive pattern providing circuit contacts providing electrical connections among the discrete circuit elements and circuit contacts providing electrical connections to components external to the attenuator. The second surface includes a second electrically conductive pattern.

Abstract: A signal conditioning system includes first and second converters coupled to a random clock which provides a random sampling rate. Corresponding offset sensor coupled with the first and second converters sense and adjust an offset signal difference. A gain sensor is coupled with the first and second converters to sense a gain difference between the first and second converters and a gain corrector is coupled with the gain sensor to adjust the gain difference.

Abstract: The number of components of a high frequency power amplifier is reduced. A bias resistance ratio is adjusted in accordance with a change in the threshold voltage Vth of a transistor. A high frequency power amplifier has a plurality of amplifying systems. Each of these systems has an input terminal to which a signal to be amplified is supplied, an output terminal, a bias terminal, a plurality of amplifying stages which are sequentially cascaded between the input and output terminals, and a bias circuit connected to the bias terminal and each of the amplifying stages to apply a bias potential to the amplifying stage. The amplifying stage includes a control terminal for receiving an input signal and the bias potential supplied to the stage and a first terminal for transmitting an output signal of the stage.

Abstract: Binarization a data value comprises binarizing the minimum of the data value and a predetermined cut-off value in accordance with a first binarization scheme, in order to yield a primary prefix. If the data value is greater than the cut-off value, binarizing a difference of the data value minus the predetermined cut-off value in accordance with a second binarization scheme to obtain a binary suffix, the first binarization scheme being different from the second binarization scheme, and appending the primary suffix to the primary prefix is performed. A very effective compression of data values may be achieve by using the binarization scheme for preparing the syntax elements for the arithmetic coding, the binarization schemes substantially being a combination of two different binarization schemes, and by using binary arithmetic coding instead of m-ary arithmetic coding for coding the binarized syntax elements.

Abstract: An A/D converter converts a sine and cosine wave output of a resolver to form a digital sine and cosine. A microcomputer uses an absolute value of digital sin ? as an address to retrieve ? from a memory containing angle values between 0° and 90°, if the absolute value of sin ? is between 0 and 0.707. Otherwise, if the absolute value of sin ? is between 0.707 and 1, cos ? is used as an address to retrieve ?. The polarities of sin ? and cos ? are used to determine a quadrant and an associated offset including 0°, 180°??, 180°+?, and 360°??, which is combined with ? such that the final angle of the rotor axis is obtained.

Abstract: An pipeline analog-to-digital converter (ADC) is provided that is capable of applying calibration at a resolution greater than the resolution of a digital output signal provided by the ADC. The ADC includes a calibration component adapted to apply calibration bits to digital output bits generated by stages of the pipeline and corresponding to samples of an analog input signal. The ADC also includes a random number generator that provides at least one random bit having a sub-LSB bit weight. The calibration bits and the at least one random bit are applied as a dither to the digital output bits such that, on average, the digital output signal provided by the ADC is calibrated at a sub-LSB resolution.

Abstract: A monolithic non-linear transmission line and sampling circuit with reduced shock-wave-to-surface-wave coupling are presented herein. In coplanar-waveguide (CPW) technology, this reduced coupling is achieved by selecting properly the thickness of the semiconductor substrate, and by elevating the center conductor of the CPW above the substrate surface. The elevated center conductor is supported by means of conducting posts, and may be backed by a low-loss dielectric such as polyimide or silicon nitride. In coplanar-strip (CPS) technology, the reduction in coupling between shock waves and surface waves is achieved by controlling the substrate thickness as in the CPW case, and by elevating the coplanar strips above the substrate surface. The elevated strips are supported by a low-loss dielectric. The reduced coupling in both guiding media enhances the high-frequency performance of nonlinear-transmission-line-based circuits.

Abstract: A method for correcting A/D converted output data which corrects digital data obtained by A/D conversion of an analog signal, comprising forming an at least first order polynomial curve approximating an input/output characteristic curve of A/D conversion in a range of input of the analog signal, setting an ideal input/output characteristic line of A/D conversion, deriving a conversion equation for converting coordinates of a point on the approximation polynomial curve to a point of the ideal input/output characteristic line for the same analog signal value, and using this conversion equation to convert A/D converted digital data so as to correct non-linearity of the output data.

Abstract: A pipelined analog-to-digital converter features an amplifier block that includes a switching network to implement a double sampling and double conversion principle of operation. The amplifier block utilizes both phases of a clock for sampling and conversion. Additionally, each stage of the analog-to-digital converter is associated with two independent processing blocks. The analog-to-digital converter can achieve double throughput for approximately the same level of power consumption. Alternatively, throughput may be maintained, but the gain-bandwidth of the amplifier block may be reduced by half, thereby halving the DC bias current consumed by the amplifier. Additionally, the output signal of the amplifier itself is not reset to a common mode voltage.

Abstract: A method and apparatus to estimate a motion using searched motion vectors, and an image encoding system adopting the method and apparatus are provided. The motion between lower level frame data is estimated to obtain search points with minimum Sum of Absolute Differences (SADs). The search points are used as a based motion vector. Searches are performed on both upper level frame data and upper level field data using the based motion vector and search points are obtained with minimum SADs. The search points obtained from the searches on the upper level frame data and upper level field data are used as frame and field motion vectors.

Abstract: An input/output buffer. An input/output circuit is composed of a first PMOS transistor and a first NMOS transistor, has an I/O port coupled to an I/O pad, and a N-well region. An N-well control circuit controls the voltage level at the N-well region of the first PMOS transistor according to input signals at the I/O pad. A P-gate control circuit receives a second gate control signal and outputs to the gate of the first PMOS transistor. The P-gate control circuit is composed of a transmission gate and a third PMOS transistor. The transmission gate and the third PMOS transistor do not have to follow the design rule for ESD, and the wafer area required for the P-gate control circuit can be decreased because the P-gate control circuit is not directly connected to the I/O pad.

Abstract: An electronic device having a current switch type driver is provided. The current switch type driver includes a differential circuit that supplies a current to a transmission channel according to a signal. In the electronic device, a signal wire that transmits the signal to the differential circuit has a transmission channel structure.

Abstract: Methods and systems for filtering an analog signal sampled at a very high frequency and outputting a digital signal that has a very low sampling frequency to drive a material metering machine. The high frequency digital input signal is input to a first decimation element, which filters out the noise in the signal introduced by an analog-to-digital (A/D) converter and reduces the sampling frequency of the digital signal to a lower sampling frequency of 1200 hertz. The reduced rate digital signal is input into a second decimation element that contains several decimation filters, which reject the 60 hertz line noise and its harmonics while simultaneously reducing the sampling frequency of the digital signal to 10 hertz. The output of the second decimation element is then passed to a bank of selectable filters with sub-hertz cutoff frequencies to remove the machine noise from the material metering machine.

Abstract: A system and method to modulate coding based on an ECC interleave structure include a first encoder encoding an input stream of bits comprising input blocks sorted into interleaves. A second encoder encodes a subset of the input blocks to produce output blocks, where the first encoder permutates a remainder of the input blocks and the output blocks to produce a codeword.