Patents Examined by Jeffery S Zweizig
  • Patent number: 10469076
    Abstract: Combining the functionality of sleep transistors with logic devices in power-gating circuits by utilizing fully depleted silicon-on-insulator (FDSOI) transistors. In an embodiment, a back gate of a FDSOI transistor controls the threshold voltage to eliminate the need for standalone sleep transistors.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 5, 2019
    Assignee: The Curators of the University of Missouri
    Inventors: Masud H. Chowdhury, Emesahw Ashenafi
  • Patent number: 10444785
    Abstract: A system and method quadrature clock generation circuit includes an approximate quadrature clock generator and an I/Q correction circuit. The approximate quadrature clock generator has an input configured to receive an input signal and generate an approximate quadrature clock and an approximate in-phase clock using the input signal. The I/Q correction circuit is configured to receive the approximate quadrature clock at a first quadrature input and the approximate in-phase clock at a first in-phase input and output an improved quadrature clock at a first quadrature output and improved in-phase clock at a first in-phase output.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: October 15, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Valentin Abramzon
  • Patent number: 10437271
    Abstract: Systems and apparatuses for a configurable, temperature dependent reference voltage generator are provided. An example apparatus includes control logic configured receive temperature data, and produce a signal, based on the temperature data, indicative of the temperature data, a temperature dependence and a temperature slope. The apparatus may also include a temperature slope reference generator configured to produce a reference voltage having the temperature dependence and the temperature slope, based on the signal from the control logic.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yuanzhong Wan, Dong Pan
  • Patent number: 10439622
    Abstract: According to one embodiment, there is provided a transmission device including a digital PLL and a power amplifier. The power amplifier is connected to the digital PLL. The digital PLL includes a digital oscillator and a controller. The controller operates the digital oscillator with a first loop bandwidth in a first period corresponding to startup of the power amplifier, operates the digital oscillator with a second loop bandwidth narrower than the first loop bandwidth in a second period being after the first period, and operates the digital oscillator with a third loop bandwidth narrower than the second loop bandwidth in a third period being after the second period.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 8, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yuki Tsuda
  • Patent number: 10431867
    Abstract: One embodiment includes a clock distribution system. The system includes a first resonator spine that propagates a first clock signal and a second resonator spine that propagates a second clock signal that is out-of-phase relative to the first clock signal. The system also includes at least one resonator rib each conductively coupled to at least one of the first and second resonator spines and being arranged as a standing wave resonator with respect to a respective at least one of the first and second clock signals to inductively provide the respective at least one of the first and second clock signals to an associated circuit via a respective transformer-coupling line. The system further includes an isolation element configured to mitigate at least one of inductive and capacitive coupling between the first and second clock signals.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 1, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Joshua A. Strong, Max E. Nielsen, Peter John Andrews
  • Patent number: 10432185
    Abstract: A system includes a storage capacitor coupled between an input voltage source and a ground terminal, a voltage sensing circuit coupled to the input voltage source and to the storage capacitor, a first transistor coupled to the voltage sensing circuit, a current mirror circuit coupled to the first transistor, a diode coupled between the storage capacitor and the current mirror circuit, and a second transistor configured to couple between a gate of a power switching device and the ground terminal. A gate of the second transistor is coupled to the storage capacitor by way of the voltage sensing circuit.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: October 1, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Jae Won Choi, Richard Turkson
  • Patent number: 10432080
    Abstract: A driving device of a semiconductor device includes a plurality of protection factor detection units, an identification signal generation unit, a continuation signal generation unit, a signal selection unit, and an alarm signal output unit. The protection factor detection units detect an occurrence of a protection factor. The protection factor requires a protection operation of a semiconductor device. The protection factor detection units output a protection factor generation signal. When any protection factor detection units output the protection factor generation signal, the identification signal generation unit generates a protection factor identification signal. The continuation signal generation unit generates a protection factor continuation signal while the protection factor detection unit outputs the protection factor generation signal. The signal selection unit selects the protection factor identification signal and the protection factor continuation signal.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: October 1, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kenshi Terashima
  • Patent number: 10425072
    Abstract: An output circuit outputs communication signals and communicates with an external device ED, and includes: a PNP first transistor, which is capable of outputting a collector current as the communication signals; and a first current source, which is capable of changing a base current of the first transistor, and which reduces the base current to a predetermined current value after the first transistor is turned on and before the first transistor is turned off.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 24, 2019
    Assignee: OMRON Corporation
    Inventors: Kazuaki Miyamoto, Ryota Hasegawa, Hiroyuki Tsuchida
  • Patent number: 10425073
    Abstract: A digital active diode circuit for letting current pass in one direction and substantially blocking current in the opposite direction is presented. The circuit contains switching means comprising an array of switches, a first comparison unit coupled to the digital active diode circuit input and output. The first comparison unit updates its output if the difference between their inputs is higher than a first threshold voltage, and a second comparison unit being coupled to the digital active diode circuit output and input. The second comparison unit updates its output if the difference between its inputs is lower than a second threshold voltage. The switching means switches on or off at least one switch based on the comparisons performed by the first comparison unit and the second comparison unit and wherein the first threshold voltage is different from the second threshold voltage.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 24, 2019
    Assignee: Dialog Semiconductor B.V.
    Inventors: Marinus Wilhelmus Kruiskamp, Petrus Hendrikus Seesink
  • Patent number: 10424942
    Abstract: A wireless power transfer system comprises: a transmitter comprising a transmit electrode set configured to transfer power via resonant electric field coupling; and a receiver comprising a receive electrode set configured to extract the transferred power via resonant electric field coupling, wherein the electrodes of at least one of the transmit and receive electrode sets are concentric.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: September 24, 2019
    Assignee: SOLACE POWER INC.
    Inventors: Magnus Nyberg, Andrew Bartlett
  • Patent number: 10418983
    Abstract: A duty cycle correction circuit is provided. The duty cycle correction circuit may include a correction circuit configured to correct a duty cycle of an external clock signal according to a locking signal. The duty cycle correction circuit may include a locking signal detection circuit configured to generate the locking signal for correcting the duty cycle of the external clock signal, using an internal clock signal generated in a semiconductor circuit.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyun Bae Lee
  • Patent number: 10418076
    Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Pascal A. Meinerzhagen, Stephen T. Kim, Anupama A. Thaploo, Muhammad M. Khellah
  • Patent number: 10411697
    Abstract: A voltage detection circuit is disclosed. The voltage detection circuit includes a threshold voltage detection circuit, a current leakage compensation circuit and a low voltage detection circuit. The threshold voltage detection circuit detects the voltage of a power source and determines whether the voltage is dropped over a threshold voltage, so as to wake up the low voltage detection circuit. The current leakage compensation circuit determines whether a voltage difference between the first voltage and the second voltage exceeds a preset value, so as to generate a trigger signal to activate the low voltage detection circuit. As a result, the voltage detection circuit can have high efficiency and low power consumption, and can detect the voltage drop more accurately in environment with current leakage, temperature variation, or process variation.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: September 10, 2019
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Po-Sheng Chen, Yeh-Tai Hung
  • Patent number: 10410701
    Abstract: A clock monitoring circuit includes: a sampling circuit suitable for sampling a monitoring target clock in synchronization with a sampling clock; a first counter circuit suitable for counting the number of times that the sampling circuit samples the monitoring target clock at a predetermined level; and a second counter circuit suitable for counting the number of times that the sampling circuit performs sampling.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventors: Myeong-Jae Park, Young-Jae Choi
  • Patent number: 10401404
    Abstract: Disclosed are various approaches for measuring and reporting the amount of electrical power consumed by an electrical load attached to a guided surface wave receive structure. A guided surface wave receive structure is configured to obtain electrical energy from a guided surface wave traveling along a terrestrial medium. An electrical load is coupled to the guided surface wave receive structure, the electrical load being experienced as a load at an excitation source coupled to a guided surface waveguide probe generating the guided surface wave. An electric power meter coupled to the electrical load and configured to measure the electrical load.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 3, 2019
    Assignee: CPG Technologies, LLC
    Inventors: James F. Corum, Kenneth L. Corum, Joseph F. Pinzone, James D. Lilly, Michael W. Miller, Stephen W. Wilson
  • Patent number: 10388848
    Abstract: Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Lester Lampert, Ravi Pillarisetty, Hubert C. George, Kanwaljit Singh, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, David J. Michalak
  • Patent number: 10381923
    Abstract: An electronic device includes a reconfigurable charge pump including pump units that can be arranged differently for varying an output voltage generated by the reconfigurable charge pump; a pump regulator coupled to the reconfigurable charge pump, the pump regulator configured to monitor the output voltage and turn the reconfigurable charge pump on or off based on the output voltage; and an arrangement control mechanism coupled to the pump regulator, the arrangement control mechanism configured to control operation of the pump regulator based on the output voltage to generate arrangement control output, wherein the arrangement control output controls electrical connections between the pump units.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo, Qiang Tang
  • Patent number: 10374600
    Abstract: First and second comparators receive input signals of opposed polarities and drive operation of a switch in response thereto. A first current generator supplies a first current to the switch which, in response to the control of the first and second comparators, applies the first current, alternatively, to a first node or a second node. A second current generator sinks a second current from the first node and a third current generator sinks a third current from the second node. A logic circuit has inputs coupled to the first node and the second node, respectively, receives respective switching signals having fast switching wavefronts and delayed switching wavefronts. The output of logic circuit is configured for switching between a first state and a second state with switching between the first state and the second state triggered by the fast switching wavefronts of the respective switching signals.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 6, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ignazio Bruno Mirabella, Agatino Antonino Alessandro
  • Patent number: 10374584
    Abstract: An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Muhammad Khellah, Arvind Raman, Feroze Merchant, Ashish Choubal
  • Patent number: 10367356
    Abstract: An inverter energy system supplies power to a site. The inverter energy system comprises a number of solar strings, each solar string including a solar panel(s) as a renewable energy source and an inverter. The inverter energy system is connected to a mains power supply (grid) and to a site load (sub circuits). The forward or reverse power flow into or out of the mains power supply is monitored at a monitoring point at the site. A rate limit is set for power flow into and/or or out of the mains power supply. The supply of power from the inverter energy system is controlled so that the power flow into or out of the mains power supply is within the set rate limit.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: July 30, 2019
    Assignee: Honey Badger International PTY Ltd.
    Inventor: Gregory Neville Rogers