Abstract: A semiconductor device that outputs a reset signal for controlling a reset operation of a reset target circuit connected to a first power supply and a second power supply having a voltage lower than a voltage of the first power supply, the semiconductor device including: a power supply voltage monitoring circuit connected to the first power supply and the second power supply, the power supply voltage monitoring circuit monitors the voltage of the first power supply, wherein the power supply voltage monitoring circuit includes a first transistor having a first conductive type and a second transistor having a second conductive type different from the first conductive type, and wherein the reset signal is switched when the voltage of the first power supply is equal to or greater than a sum of a threshold voltage of the first transistor, and a threshold voltage of the second transistor.

Abstract: According to at least one aspect, a controller having a mode of operation including one of an on mode and an off mode is provided including a voltage supply node, a mode of operation signal node, a powered component, a switching device coupled in series between the voltage supply node and the powered component, a power supply detector coupled to the switching circuit, the voltage supply node, and the mode of operation signal node, the power supply detector being configured to receive a mode of operation signal indicative of the mode of operation of the controller from the mode of operation signal node, determine that the controller is in the off mode based on the mode of operation signal, and control the switching device to prevent a current from passing from the voltage supply node to the powered component responsive to determining that the controller is in the off mode.

Abstract: A three-level converter includes a high-voltage side unit, a low-voltage side unit, a flying capacitor, a first switch to a fourth switch, and a control unit. When a voltage of the flying capacitor falls outside a safe target voltage range, the control unit may control the third switch and the fourth switch to be normally open, and control, based on the voltage of the flying capacitor and a voltage of the low-voltage side unit, each of the first switch and the second switch to be turned on or off, so that the voltage of the flying capacitor falls within the target voltage range. Alternatively, the control unit may control the first switch and the second switch to be normally open, and control, based on the voltage of the flying capacitor and a voltage of the low-voltage side unit.

Abstract: A regulated charge pump includes a comparator having a first input coupled to an output of the regulated charge pump, a second input configured for receiving a reference voltage, and an output for generating an output voltage representing a difference between a charging current of the regulated charge pump and a load current of a load coupled to the output of the regulated charge pump; a first converter having an input coupled to the output of the comparator, and an output connected to a control bus configured to indicate an adjustment of the charging current in response to the comparator output; and a driving stage having a first input coupled to the control bus, and an output for providing the charging current, wherein the output of the driving stage comprises the output of the regulated charge pump.

Abstract: A charge pump circuit is provided, comprising: a first charge pump having an input terminal for receiving a supply voltage and configured to boost the received supply voltage to provide at an output terminal of the first charge pump a first charge pump voltage; a second charge pump having an input terminal coupled to the output terminal of the first charge pump for receiving the first charge pump voltage and configured to boost the received first charge pump voltage to provide at an output terminal of the second charge pump a second charge pump voltage, and a voltage drop sensing device configured to detect drops in the first charge pump voltage and to deactivate second transistors of bypass units associated to the disabled charge pump stages when a drop in the first charge pump voltage is detected.

Abstract: The present disclosure relates to systems and methods for clock synchronization. The system may include a reset signal generator connected with a plurality of detectors. The reset signal generator may be configured to generate a set of preliminary reset signals to be detected and transmit the set of preliminary reset signals to the plurality of detectors. Each of the set of preliminary reset signals may have a different phase. Each of the plurality of detectors may be configured to generate first feedback data for each of the set of preliminary reset signals and transmit the first feedback data to the reset signal generator. The reset signal generator may be further configured to generate, for each of the plurality of detectors, a reset signal based on the first feedback data and transmit the reset signal to each of the plurality of detectors. Each of the plurality detectors may be further configured to execute a clock synchronization in itself based on the reset signal.

Abstract: A temperature sensor includes a sensing element and a load. Multiple different currents pass through the sensing element in a sequential manner. Based on each current that passes through the sensing element, the sensing element outputs a complementary-to-absolute-temperature (CTAT) voltage and another current. Further, the currents that pass through the sensing element and the currents that the sensing element output separately pass through the load and result in the generation of multiple load voltages across the load. A current density ratio of the temperature sensor is determined based on the load voltages generated across the load. Further, a temperature value indicative of a temperature sensed by the temperature sensor is generated based on the current density ratio and the CTAT voltages outputted by the sensing element based on the different currents that pass therethrough.

Abstract: The present invention concerns a method and a device for increasing the reliability of a power module composed of plural power semiconductors that are connected in parallel, the power semiconductors being connected to the external pins of the package of the power module through metallic connections. The invention: —selects one power semiconductor among the power semiconductors connected in parallel according to a criterion, —applies a same input patient to the not selected power semiconductors connected in parallel, —increases the temperature of the selected power semiconductor in order to reach a target temperature of the power semiconductor during a time duration in order to achieve and interface grain homogenisation of the metallic connections of the selected power semiconductor, —applies the same input pattern to the selected power semiconductor after the time duration.

Abstract: An electronic component includes circuits that function independently of one another, and a switch electrically connected to the circuits. The electronic component includes a base body and two or more input/output terminals. The base body includes a main surface. The two or more input/output terminals are provided to the main surface of the base body, and include two first input/output terminals adjacent to each other. The switch changes one of the two first input/output terminals adjacent to each other to a hot terminal and changes the other to a ground terminal.

Abstract: A voltage conversion apparatus for converting from a control voltage to a supply voltage and an apparatus for converting from a supply voltage to a control voltage are described. The supply voltage is designed to power, through a coaxial cable, a data communication device, and the coaxial cable is suitable for transmitting said supply voltage signal and at least one data signal associated with said data communication device. A conversion means of the conversion apparatus is configured to convert from the control voltage to the supply voltage comprising conversion means configured to convert from a first value of control voltage Vp1 and from a second value of control voltage Vp2 to a first value of supply voltage Va1 and, respectively, to a second value of supply voltage Va2. Said first value of control voltage Vp1 and said second value of control voltage Vp2 are values of control voltage for controlling a device that is distinct from such a data communication device.

Abstract: Provided is a circuit including a switching transistor having a control terminal configured to receive a control signal and having a current flow path therethrough. The switching transistor becomes conductive in response to the control signal having a first value. The current flow path through the switching transistor provides a current flow line between two nodes. In a non-conductive state, a voltage drop stress is across the switching transistor. The circuit comprises a sense transistor that is coupled to and a scaled replica of the switching transistor. The sense transistor has a sense current therethrough. The sense current is indicative of the current of the switching transistor. The circuit includes coupling circuitry configured to apply the voltage drop stress across the sense transistor in response to the switching transistor being non-conductive. In the non-conductive state, the voltage drop stress is replicated across both the switching transistor and the sense transistor.

Abstract: A method includes providing, by a signal source circuit of a sensing circuit, a signal to a sensor via a conductor. When the sensor is exposed to a condition and is receiving the signal, an electrical characteristic of the sensor affects the signal. The signal includes at least one of: a direct current (DC) component and an oscillating component. When the sensing circuit is in a noisy environment, transient noise couples with the signal to produce a noisy signal. The method further includes comparing, by a transient circuit of the sensing circuit, the noisy signal with a representation of the noisy signal. When the noisy signal compares unfavorably with the representation of the noisy signal, supplying, by the transient circuit, a compensation signal to the conductor. A level of the compensation signal corresponds to a level at which the noisy signal compares unfavorably with the representation of the noisy signal.

Abstract: Systems and methods for switching between a power supply mode and an electronic load mode are disclosed. For switching from the power supply mode to the electronic load mode, the method comprises the steps of: deactivating a power element; activating a current control module and a phase-locked loop to obtain a voltage phase of a device under test; calculating a turn-on amount of the power element according to a current setting value and the voltage phase; and causing the power element to generate a load current for the device under test. For switching from the electronic load mode to the power supply mode, the method comprises the steps of: deactivating the power element; activating a voltage control module; calculating the turn-on amount of the power element according to a voltage setting value; and causing the power element to input a corresponding voltage to the device under test.

Abstract: In one aspect, a time division interleaving band-pass filter can be used in voice activity detection, which operates at different central frequencies in respective intervals of a predetermined period of time. The band-pass filter circuitry includes multiple band-pass filtering channels sharing a common transistor circuit, bias circuit and current mirror circuit. The multiple band-pass filtering channels operate in a time division interleaving manner, which enables the sharing of the common set of band-pass filter circuitry components. Thus, the present invention allows a reduced chip area as the area does not increase proportionally with the number of filtering channels. The invention also mitigates the influence of transistor fabrication variations on the filter's central frequencies.

Abstract: A bandgap reference circuit generates a PTAT voltage and a CTAT voltage having a different temperature characteristic from the PTAT voltage and generates a reference voltage based on the PTAT voltage, the CTAT voltage, and a compensation voltage. The bandgap reference circuit generates a CTAT current having a different temperature characteristic from the PTAT voltage based on the CTAT voltage and determines the compensation voltage based on the CTAT current.

Abstract: In described examples, a circuit includes a switch. The switch includes first transistors and second transistors. A voltage generation circuit is coupled to the switch. A level shifter is coupled to the voltage generation circuit and is configured to receive a control signal. A logic unit is coupled to the level shifter and the voltage generation circuit. The logic unit is configured to generate a secondary signal. The first transistors are configured to receive the control signal, and the second transistors are configured to receive the secondary signal.

Abstract: A curvature compensated bandgap circuit that is capable of matching best-in-class two (2) parts-per-million performance without over-temperature trimming. This improves performance metrics for precision voltage reference products without requiring individual device tuning during production thereof. A core bandgap circuit comprises a main operational amplifier having a second order bowed voltage response over temperature. A ptat circuit is coupled to the core bandgap circuit to provide a sigmoidal third order shape for the bandgap voltage.

Abstract: Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.

Abstract: Circuits/methods for controlling the startup of multiple parallel power converters that avoid inrush current or switch overstress in an added power converter or a power converter having fault conditions. Embodiments include node status detectors coupled to nodes within parallel-connected power converters to monitor voltage/current and configured in some embodiments to work in parallel with an output status detector measuring the startup output voltage of a power converter. With charge pump-based power converters, the node status detectors ensure that the power converter pump capacitors are charged while the output capacitor is charged as well. For such embodiments, a softstart period of startup may be considered finished if both the shared output capacitors and the power converter pump capacitors are charged to target values. Embodiments may also be used for fault detection during steady-state operation.

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.