Abstract: A computing device and a driving method thereof are provided. The computing device is a computing device having a main board with a plurality of elements, and includes a linear regulator unit including a plurality of linear regulators configured to convert a voltage from a power supply into different voltages required for the plurality of elements and apply the different voltages, and a femto-clock generation unit including a plurality of femto-clock generators configured to generate femto-clocks of different frequencies to be used for control of operations of the plurality of elements.

Abstract: A linear power supply circuit is provided with: an output transistor; and a driver for driving the output transistor on the basis of the difference between a voltage based on an output voltage and a reference voltage. The driver is provided with: a differential amplifier for outputting a voltage according to the difference between the voltage based on the output voltage and the reference voltage; a capacitor one end of which has an output of the differential amplifier applied thereto and the other end of which has the voltage based on the output voltage applied thereto; a converter for converting a voltage based on the output of the differential amplifier into an electrical current and outputting the electrical current; and a current amplifier for amplifying the electrical current of the output of the converter. The supply voltage of the differential amplifier is a first constant voltage or the input voltage.

Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.

Abstract: A method of operating a system including a parameter monitoring circuit and a host, includes generating a first parameter applying a first code to a current parameter, wherein a first offset is applied to the first code; generating a first comparison result by comparing the first parameter with a reference parameter value; generating a second parameter applying a second code to the current parameter, wherein a second offset is applied to the second code; generating a second comparison result by comparing the second parameter with the reference parameter value; detecting an error in the current parameter, based on the first comparison result and the second comparison result; and providing a signal based on the error to the host.

Abstract: A multi-input single output power system for outputting an output voltage on an output node. It includes a first integrated circuit (IC) converter device and a second IC converter device. The first IC converter device has a first pin to receive a first input voltage, a second pin to output the output voltage, and a first power unit coupled between the first pin and the second pin. The second IC converter device has a first pin to receive a second input voltage, a second pin to output the output voltage, a second power unit coupled between the first pin of the second IC converter device and the second pin of the second IC converter device, and a third pin. The third pin receives an external phase shedding control signal to determine whether to stop the second power unit from providing power to the output node.

Abstract: A power source switching circuit is disclosed. The power source switching circuit includes a voltage regulator, a first transistor and a second transistor. The first transistor is coupled with a first voltage source and the second transistor is coupled with a second voltage source. The voltage regulator includes a resistor, one or more diodes coupled together in series and a capacitor. Terminals of the capacitor are coupled between a gate and a source of the first transistor through a first switch and a second switch respectively. The capacitor is configured to hold charge to switch the first transistor on. A value of the capacitor is smaller than a gate to source capacitance of the first transistor.

Abstract: A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.

Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).

Abstract: A semiconductor apparatus includes a first clock path which generates a first output clock signal by delaying a first phase clock signal, and a second clock path which generates a second output clock signal by delaying a second phase clock signal based on a delay compensation signal. The oscillating path generation circuit forms oscillating paths with the first clock path and the second clock path. The delay information generation circuit generates a delay compensation signal based on oscillating signals generated by forming the oscillating paths.

Abstract: The present disclosure provides a differential reference voltage buffer, including: a buffer stage, including at least a first transistor and a second transistor; a control circuit, connected with the buffer stage and forming a negative feedback structure for generating a differential reference voltage; a current compensation circuit for compensating a resistive load current of the control circuit; and a drive stage for generating an output differential reference voltage. The differential reference voltage is generated according to an external input reference voltage and a common mode input voltage. The common mode voltage can be set separately, so that the flexibility is high. The current generated by a resistive network in the control circuit is compensated by the current compensation circuit, so that the current of a follow device in the buffer stage is not influenced by the control circuit, thereby generating a differential reference voltage with high accuracy output.

Abstract: Systems and methods are described for controlling inrush current for a system comprising a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs). The system may include a control circuit coupled to parallel series of gate drivers, where each gate driver is coupled to a different MOSFET. An inrush current may be received during charging of a capacitor of the switch circuit. During a first period of a ramp time, the control circuit may cause the inrush current to pass through a first gate driver. During a second period of the ramp time, the control circuit may cause the inrush current to pass through a second gate driver. By using a control circuit to cause the inrush current to pass through each MOSFET, a gate-source threshold voltage for the MOSFETs may remain below safe operating areas (SOAs) for the different MOSFETs.

Abstract: A power-on reset circuit includes a complementary-to-absolute-temperature circuit that outputs one control voltage, and a proportional-to-absolute-temperature (PTAT) circuit that outputs a PTAT current. The power-on reset circuit further includes various resistors that are coupled in series, and generate another control voltage based on the PTAT current that is outputted by the PTAT circuit. Further, the power-on reset circuit includes a comparator that compares the two control voltages to generate a power-on reset signal. The power-on reset signal is activated when a supply voltage is greater than or equal to a trip voltage, and deactivated when the supply voltage is less than the trip voltage. A functional circuit is configured to execute a reset operation associated therewith when the power-on reset signal transitions from a deactivated state to an activated state.

Abstract: Driver circuitry for driving a load based on an input signal, comprising: at least one variable boost stage comprising: first and second input nodes configured to receive a first voltage and a second voltage respectively; first and second flying capacitor nodes for connection to a flying capacitor therebetween; a network of switching paths for selectively connecting the first and second input nodes with the first and second flying capacitor nodes; an output stage for selectively connecting a driver output node to each of the first and second flying capacitor nodes; and a controller operable in a first boost mode to: control the output stage to selectively connect the driver output node to the first flying capacitor node; control the network of switching paths to switch connection of the second flying capacitor node between the first and second input nodes at a controlled duty cycle; and in a first charge top-up cycle, control the network of switching paths to connect the first input node to the first flying c

Abstract: An integrated circuit has a CMOS signal path coupled for receiving a data signal. A compensation circuit is coupled to a power supply rail of the CMOS signal path for injecting a compensation current into the power supply rail. The compensation circuit can be a charge pump operating in response to the data signal to inject the compensation current into the power supply rail each transition of the data signal. The compensation circuit can be a replica CMOS signal path to inject the compensation current into the power supply rail each transition of the data signal. The compensation circuit can be a voltage regulator and current mirror including an input coupled to the voltage regulator. The replica CMOS signal path receives an operating potential from the voltage regulator. An output of the current mirror injects the compensation current into the power supply rail each transition of the data signal.

Abstract: A voltage regulator circuit comprises a regulator output; an amplifier that is activated in response to a first signal and inactivated in response to a second signal, the error amplifier having a first input for receiving a reference voltage, a second input for receiving a feedback voltage, and an output that generates a differential with respect to the reference voltage and the feedback voltage; an active discharging transistor that, in response to a falling slope of the electronic signal, discharges a present electronic signal at the regulator output; and a first switch at the output of the amplifier that is in open state in response to a receipt of the second signal to disconnect a coupling capacitor path between the regulator output and the reference voltage to negate an effect of noise on the reference voltage in response to the falling slope of the electronic signal.

Abstract: A semiconductor device capable of level shifting in a negative potential direction using an n-channel transistor is provided. The semiconductor device includes a first source follower, a second source follower, and a comparator. The first source follower is supplied with a second high power supply potential and a low power supply potential; the second source follower is supplied with a first high power supply potential and the low power supply potential; and a digital signal which expresses a high level or a low level using the second high power supply potential or the first high power supply potential is input to the first source follower. Here, the second high power supply potential is a potential higher than the first high power supply potential, and the first high power supply potential is a potential higher than the low power supply potential.

Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.

Abstract: Aspects of the disclosure are directed to adaptively delaying an input signal. In accordance with one aspect, an apparatus includes a plurality of delay units, wherein each of the plurality of delay units includes a substantially similar output load characteristic; a plurality of buffer units, wherein each of the plurality of buffer units is coupled to one of the plurality of delay units; wherein a quantity of the plurality of delay units equals a quantity of the plurality of buffer units; an additional delay unit coupled to a delay unit output of one of the plurality of delay units; and a one-hot decoder coupled to each of the plurality of buffer units, the one-hot decoder configured to enable one and only one of the plurality of buffer units.

Abstract: An electrical circuit for ensuring safe ramp-up and ramp-down of at least a regulated operating voltage, a reference voltage, and a reset signal for a consumer is described. The electrical circuit includes a voltage reference circuit and a voltage regulator. The voltage regulator is provided in order to furnish a regulated operating voltage, the voltage reference circuit is provided in order to be supplied with the regulated operating voltage furnished by the voltage regulator, and the voltage regulator is provided in order to obtain a reference voltage from the voltage reference circuit.

Abstract: An embodiment voltage-current converter circuit comprises a first amplifier and a second amplifier having homologous first input nodes configured to receive a voltage signal therebetween as well as homologous second input nodes having a resistor coupled therebetween. First and second current mirror circuits are provided comprising first input transistors having their control terminal coupled to the output nodes of the amplifiers. First and second current sensing circuitry having first and second current output nodes are coupled to the current mirror output nodes of the current mirror circuits and configured to provide therebetween a current which is a function of the voltage signal between the homologous first input nodes of the amplifier.