Abstract: A regulator circuit and a front-end module including the same may be disclosed. The regulator circuit may include a first output voltage generator and a second output voltage generator. The first output voltage generator may include a first resistor having a first end connected to power supplied from an outside, a first transistor connected between a second end of the first resistor and a ground terminal to supply a first voltage, and a second transistor receiving the first voltage through a control terminal and outputting a first output voltage through a first terminal. The second output voltage generator may be connected between the power and the first output voltage generator to output a second output voltage obtained by adding a predetermined voltage into the first output voltage.

Abstract: The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.

Abstract: Various embodiments relate to a level shifter circuit configured to generate a voltage output, including: a first charging path circuit; a second charging path circuit; and an enable circuit configured to enable the first charging path circuit and the second charging path circuit, wherein the voltage output is a combination of the voltage from the first charging path circuit and the second charging path circuit, the first charging path circuit charges up to a voltage limit, and the first charging path circuit charges the voltage output faster than the second charging path circuit.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.

Abstract: A power supply control circuit that is able to reliably discharge to the internal power supply, even when the external power supply is cut off instantaneously. The power supply control circuit includes a voltage detection unit, an internal power supply generation unit, and a control unit. The voltage detection unit detects the voltage of the external power supply. The internal power supply generation unit generates the internal power supply, according to the external power supply. The control unit controls the discharging to the internal power supply according to at least the second control signal among the first control signal and the second control signal, when the detected voltage of the external power supply drops below the predetermined value.

Abstract: A communication device is disclosed. The disclosed communication device comprises: a transmission circuit for generating a transmission signal by using a first field effect transistor (FET) and a signal inputted from a first control circuit, and transmitting the transmission signal to a second control circuit; and a reception circuit for generating a reception signal by using a second field effect transistor (FET) and a signal received from the second control circuit, and outputting the reception signal to the first control circuit.

Abstract: The present disclosure relates to circuitry for selecting a bias voltage to output at a bias voltage output node of the circuitry. The circuitry comprises a first circuit node configured to receive a first voltage from a first, unregulated, voltage source and a second circuit node configured to receive a second voltage from a second, regulated, voltage source. A switch arrangement configured to selectively couple the bias voltage output node to the first circuit node or the second circuit node is also provided.

Abstract: Disclosed is a method for triggering the switching of a switching transistor of a quasi-resonant DC-to-DC voltage converter to the on state. The method includes the steps of phase-shifting the drain voltage of the transistor by a predetermined temporal phase-shift value that corresponds to the difference between the duration of a quarter of the period of the damped sinusoidal oscillation generated when the transistor is switched off and the period of time that elapses between the command to switch the transistor to the on state and the transistor actually conducting, and, when the phase-shifted voltage is equal to the reference voltage, triggering the command to switch the transistor to the on state such that the transistor starts conducting at the time when the value of the drain voltage is at a minimum.

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.

Abstract: A system including a power modulation device and an active voltage balancing system is provided. The power modulation device includes first and second semiconductor switches in series. The active voltage balancing system includes a differential voltage logic configured to detect a voltage difference between the first and second semiconductor switches and edge capture logic configured to detect a time difference between when the first and second semiconductor switches are switched. The active voltage balancing system further includes a micro-controller configured to output first and second gate drive signals to drive the first and second semiconductor switches. The micro-controller is configured to tune the first and second gate drive signals based on the voltage difference to compensate for voltage imbalance and the time difference to compensate for drive signal asymmetry to actively balance a voltage between the first and second semiconductor switches.

Abstract: An apparatus includes a controller. The controller controls a first power supply to produce an output current supplied through a series connection of multiple dynamic loads powered at least in part by the output current. The controller further monitors current consumption by the multiple dynamic loads. Based on the monitored current consumption, the controller adjusts a magnitude of the output current from the power supply supplied through the series connection.

Abstract: A direct-current (DC) converter for a permanent-magnet (PM) alternator for a vehicle, the DC converter including one or more pairs of step-down converters that are electrically in parallel operating at a fundamental switching frequency, wherein the two step-down converters in each pair are arranged to be switched out of phase, and wherein the two step-down converters in each pair are arranged adjacent to each other to mitigate conducted electromagnetic interference (EMI).

Abstract: Provided are a zero-crossing detection device and a method thereof, a no-neutral switch, a storage medium and a processor. The no-neutral switch may include a switch element, the switch element has a first end connected to a power supply and a second end connected to a load, and the zero-crossing detection device may include: a sampling module configured to sample a first signal of the first end of the switch element and a second signal of the second end of the switch element; a comparison module configured to compare a deviation of the first signal and the second signal with a preset threshold; and a computing module configured to compute a zero-crossing point of the power supply according to a comparison result of the comparison module and the preset threshold.

Abstract: A control device for an active filter connected in parallel with a load at an installation point with respect to an AC power supply provided in a power system includes a harmonic voltage detector to detect an m-order harmonic voltage (m is an integer not less than two) included in a voltage of the installation point, a phase corrector to correct a phase of the detected m-order harmonic voltage in accordance with whether an m-order harmonic impedance when an AC power supply side is seen from the installation point is capacitive or inductive, a command value generator to generate a first compensation command value for compensating for the m-order harmonic voltage included in the voltage of the installation point based on the m-order harmonic voltage after the correction, and an output controller to control an output of the active filter based on a first compensation command value.

Abstract: An integrated circuit (IC) includes a self-biased circuit and a start-up circuit for the self-biased circuit. The self-biased circuit generates a start-up indicator signal and an output signal. The start-up indicator signal indicates whether the self-biased circuit has started up. The start-up circuit includes a comparator, a start-up controller, and a peak controller. The comparator compares the start-up indicator signal with a reference signal generated based on supply voltages, and generates a comparison signal. The start-up controller controls a start-up of the self-biased circuit when the comparison signal is at a first logic state. Further, when the comparison signal transitions from the first logic state to a second logic state, the peak controller controls the output signal to maintain one of a voltage level and a current level of the output signal below a peak limit.

Abstract: A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.

Abstract: The present invention discloses an oscillation control circuit for an ultrasonic atomization sheet, and an ultrasonic electronic cigarette. The oscillation control circuit includes a DC boost module, a separately excited excitation module, and a microcontroller. A power module is connected to the ultrasonic atomization sheet through the DC boost module and the separately excited excitation module, and the separately excited excitation module is electrically connected to the microcontroller.

Abstract: A power-on reset circuit, including: a band-gap reference circuit, a current comparator, and a voltage comparison circuit powered by a voltage source; a first output terminal of the band-gap reference circuit connects to a control terminal of the current comparator; a first current input terminal and a second current input terminal of the current comparator receives a first current signal and a second current signal respectively, and an output terminal of the current comparator connects to a control terminal of the voltage comparison circuit; and a first input terminal of the voltage comparison circuit connects to the first output terminal of the band-gap reference circuit, a second input terminal thereof receives a signal indicating a voltage value of the voltage source, an output terminal thereof outputs a reset signal, thereby avoiding occurrence of an error caused by output of the reset signal when the reference generating circuit is unstable.

Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.