Abstract: A device for clock control and related products are provided. The device includes a voltage detecting unit and a clock stretching unit. The voltage detecting unit is configured to detect a supply voltage at a target position in the processor, and output a voltage-alarm signal when the supply voltage is lower than or equal to a preset first threshold. The clock stretching unit is connected with the voltage detecting unit and configured to generate a second clock signal according to a first clock signal having a reference frequency in response to reception of the voltage-alarm signal, such that the processor uses the second clock signal to perform data processing. A frequency of the second clock signal is lower than the reference frequency.

Abstract: According to an embodiment, an SPnT-type high frequency switch includes a plurality of first MOS transistors, second MOS transistors, and a capacitor. The plurality of first MOS transistors are connected in series between one of a plurality of RF terminals and an RF common terminal. The second MOS transistors have ends each connected to adjacent first MOS transistors among the first MOS transistors. The capacitor is connected between ground and another end of a second MOS transistor having one end connected to another end of a first MOS transistor having one end connected to the one of the RF terminals among the first and second MOS transistors.

Abstract: Methods and apparatus for filtering a signal using a current-mode filter circuit implementing source degeneration. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor comprising a drain coupled to the input node; a second transistor comprising a drain coupled to the output node and comprising a gate coupled to a gate of the first transistor; a capacitive element coupled between the drain of the first transistor and the power supply node; a first resistive element coupled between the drain and the gate of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

Abstract: A power source equipment is configured to provide a power to a powered device in a power over Ethernet. The power source equipment includes a first port, a second port, and a control circuit. The first port is configured to perform a power classification on the powered device, and provide a first voltage to the powered device in a first stage. The second port is configured to provide a second voltage to the powered device in a second stage. The control circuit is configured to disable the second port in the first stage, and configured to control the second port to output the second voltage and increase the first voltage in the second stage.

Abstract: A Marx generator has at least two branches for providing a Marx voltage at an output pole. Each of the branches has a plurality of capacitor stages with voltage poles, cross branches with spark gaps, a last capacitor stage at its output end, and a first capacitor stage connected to an operating voltage. The branches have a common triggering section with a common first capacitor stage, a first adjacent cross branch, and an input pole. Each of the branches has the triggering section and also an individual portion with at least one capacitor stage that is only associated with the branch. A resonator arrangement contains the Marx generator and resonators at the respective output poles of the branches. A radiation arrangement has the resonator arrangement and a multi-feed waveguide with at least two of the resonators for respectively feeding an electromagnetic wave.

Abstract: A high frequency variable attenuation circuit includes an input terminal, an output terminal, a first resistor, a second resistor, a third resistor, and a first switching circuit. The first switching circuit has an output side resistor and an output side switching element that are connected in series to each other. The first switching circuit has a first circuit end connected to the second end of the second resistor and the output terminal, and a second circuit end connected to the ground.

Abstract: A voltage fluctuation detection circuit includes: a source voltage decrease detection circuit configured to detect a decrease in voltage of a first power supply which outputs a first voltage and to output the result of detection as a voltage decrease detection signal using a second voltage which is lower than the voltage of the first power supply; an erroneous detection prevention circuit configured to detect an increase in voltage of the first power supply and to output the result of detection as a voltage increase detection signal using the second voltage; and a transistor configured to mask outputting of the voltage decrease detection signal in a period in which the increase in voltage of the first power supply is being detected based on the voltage increase detection signal.

Abstract: A semiconductor device according to the present disclosure includes: a first output terminal and a second output terminal; a first driver that has a first positive terminal coupled to the first output terminal and a first negative terminal coupled to the second output terminal, and outputs a differential signal corresponding to a first signal from the first positive terminal and the first negative terminal; and a second driver that has a second positive terminal coupled to the second output terminal and a second negative terminal coupled to the first output terminal, and outputs a differential signal corresponding to the first signal from the second positive terminal and the second negative terminal.

Abstract: A low-current run plug circuit comprising: a run plug configured to electrically connect 1st and 2nd terminals when the run plug is installed; a safety circuit mounted within the battery-powered apparatus comprising: a JFET a current set resistor a P-channel MOSFET, a voltage divider, and an N-channel MOSFET connected together such that when the run plug is removed the N-channel MOSFET and the P-channel MOSFET are in cutoff wherein no current flows to the electrical load, and such that when the run plug is installed, the safety circuit creates a low-impedance electrical path from the cathode to the electrical load.

Abstract: A circuit arrangement for monitoring an alternating voltage signal includes a comparator configured to receive the alternating voltage signal or a signal obtained from the alternating voltage signal at a first comparator input and output a comparator signal at a comparator output. The circuit arrangement further includes a zero crossing detector configured to receive a reference signal or a signal obtained from the reference signal at a monitoring input and generate a detector signal at an output of the zero crossing detector. The circuit arrangement further includes a logic circuit including a first timing element connected downstream of the zero crossing detector for generating a first clock signal and a second timing element connected downstream of the zero crossing detector for generating a second clock signal.

Abstract: A clock generation apparatus has a delay circuit, a phase selection circuit, and a phase measurement circuit. The delay circuit outputs a first signal that is a delayed version of an input signal. The phase selection circuit receives the input signal and one or more phase-shifted versions of the input signal and outputs a second signal that is a phase-shifted version of the input signal. The phase measurement circuit compares the phases of the first signal and the second signal and provides a first output that controls phase of the second signal relative to the input signal. The phase measurement circuit also provides a second output that controls a delay applied by the delay circuit to the input signal to generate the first signal.

Abstract: An apparatus comprises one or more A-type resistance segments, wherein each A-type resistance segment comprises one or more A-type switches, at least one A-type linear resistor coupled to the one or more A-type switches, at least one A-type tunable header unit coupled to the one or more A-type switches, and at least one A-type tunable footer unit coupled to the one or more A-type switches; one or more B-type resistance segments, wherein each B-type resistance segment comprises one or more B-type switches, at least one B-type linear resistor coupled to at least a proper subset of the one or more B-type switches, at least one B-type tunable header unit coupled to the one or more B-type switches, and at least one B-type tunable footer unit coupled to the one or more B-type switches; and wherein second terminals of the A-type linear resistors and the B-type linear resistors are coupled together.

Abstract: According to one embodiment, an inrush current suppression circuit includes a normally-on transistor, a normally-off transistor connected in series with the normally-on transistor, a first drive circuit that drives the normally-on transistor, a second drive circuit that drives the normally-off transistor, a diode connected between an output of the first drive circuit and an output terminal of the normally-off transistor, a first power source smoothing circuit that performs smoothing of a source current to be supplied to the first drive circuit and the second drive circuit, and a switch circuit that switches connection/disconnection of a current path passing through the first power source smoothing circuit.

Abstract: A novel semiconductor device is provided. The semiconductor device includes a mixer circuit and a bias circuit. The mixer circuit includes a voltage-to-current conversion portion, a current switch portion, and a current-to-voltage conversion portion. The bias circuit includes a bias supply portion and a first transistor. The voltage-to-current conversion portion includes a second transistor and a third transistor. The bias supply portion has a function of outputting a bias voltage to be supplied to a gate of the second transistor and a gate of the third transistor. One of a source and a drain of the first transistor is electrically connected to the gate of the second transistor and the gate of the third transistor. The first transistor is turned off when the bias voltage is supplied, and the first transistor is turned on when the supply of the bias voltage is stopped.

Abstract: An attenuating device for a bus of a controller area network bus system based on differential voltage signals. The bus has first and second bus lines, having an attenuating circuit that provides a variable electrical resistance value between the first and second bus lines and that is operable in at least three circuit states. In a first circuit state, the first and second bus lines are connected via an attenuating resistor having a first resistance value. In a second circuit state, the first and second bus lines are connected via an attenuating resistor having a second resistance value. In a third circuit state, the first and second bus lines are connected via an attenuating resistor having a third resistance value. The first resistance value is lower than the second resistance value. The second resistance value is lower than the third resistance value.

Abstract: In one embodiment, a system includes several voltage regulators configured to output several voltage levels. Each voltage regulator may correspond to a respective voltage level. The system includes a power switch bank that includes several power switches and several multiplexors. A set of power switches are coupled to each of the voltage regulators. Each power switch is coupled to at least one of the multiplexors. Each multiplexor is coupled to a respective voltage regulator. The system includes one or more loads coupled to a respective one or more power switch.

Abstract: A semiconductor chip includes a detection circuit configured to generate a discharge signal that is enabled when a voltage level of an external voltage is greater than a first set level and configured to generate a voltage control signal that is enabled when an output voltage is generated to have a voltage level of a ground voltage in a test mode, a charge discharge circuit configured to discharge charges of an output node that is included in a driving circuit when the discharge signal is enabled, and the driving circuit configured to generate the output voltage the voltage level of which rises up to a second set level by supplying charges from the external voltage to the output node in response to a driving signal a voltage level of which is decreased during an interval in which the voltage control signal is enabled.

Abstract: A drive device for driving a load includes: an inverter unit having an upper arm element and a lower arm element and converting electric power supplied to the load; and a charge pump circuit that supplies a gate voltage to the upper arm element. An output voltage of the charge pump circuit is variable according to an inverter input voltage input from an inverter input wiring to a high potential side of the inverter unit.

Abstract: A sampling circuit for a switching power supply, can include: a first sampling circuit configured to acquire a first sampling signal of a current flowing through an inductor in the switching power supply; and a second sampling circuit configured to obtain a compensation signal with a same rising slope as the first sampling signal within a turn-off delay time of a power switch in the switching power supply, and to superimpose the compensation signal on the first sampling signal to generate a second sampling signal.

Abstract: Systems and methods for synchronization of radio frequency (RF) generators are described. One of the methods includes receiving, by a first RF generator, a first recipe set, which includes information regarding a first plurality of pulse blocks for operating the first RF generator. The method further includes receiving, by a second RF generator, a second recipe set, which includes information regarding a second plurality of pulse blocks for operating a second RF generator. Upon receiving a digital pulsed signal, the method includes executing the first recipe set and executing the second recipe set. The method further includes outputting a first one of the pulse blocks of the first plurality based on the first recipe set in synchronization with a synchronization signal. The method includes outputting a first one of the pulse blocks of the second plurality based on the second recipe set in synchronization with the synchronization signal.