Patents Examined by Jeffrey S. Zweizig
  • Patent number: 11171636
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to provide phase imbalance correction. An example system includes a phase detector to obtain a first signal and generate a first output, a comparator coupled to the phase detector, the comparator to generate a second output based on the first output, and an amplifier coupled to the comparator, the amplifier to adjust a first phase response of the first signal based on the second output.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tolga Dinc, Salvatore Luciano Finocchiaro, Gerd Schuppener, Siraj Akhtar, Swaminathan Sankaran, Baher Haroun
  • Patent number: 11095215
    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: August 17, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pavol Balaz, Hongcheng Xu, Ferdinand Stettner
  • Patent number: 10985750
    Abstract: An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 20, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Yohan Joly, Vincent Binet, Michel Cuenca
  • Patent number: 10892680
    Abstract: An electronic device includes a reconfigurable charge pump including selectively connectable pump units for varying a generated voltage level. A control circuit may is configured to activate or deactivate the reconfigurable charge pump. The reconfigurable charge pump may track a duration based on activating the reconfigurable charge pump. When the duration exceeds a threshold, the control circuit may generates a signal according to the generated voltage level to reconfigure the electrical connections between the selectively connectable pump units.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo, Qiang Tang
  • Patent number: 10879883
    Abstract: In examples, an integrated circuit package comprises a pin exposed externally to the package; at least one resistor coupled to the pin at a first end of the resistor; a first transistor coupled to the at least one resistor at a second end of the resistor and coupled to a voltage source; a second transistor coupled to the at least one resistor at the second end of the resistor and coupled to a ground connection, the at least one resistor and the first and second transistors couple at a first node, the first and second transistors are of different types; and multiple comparators, each of the multiple comparators coupled to a voltage divider network and to the pin.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Huanzhang Huang, Jikai Chen, Yanli Fan, Md Anwar Sadat
  • Patent number: 10797168
    Abstract: An electronic device can include a HEMT that includes a channel layer, a barrier layer, and a gate electrode. The barrier layer can be disposed between the channel layer and the gate electrode and include a first portion, a second portion, and a third portion. The second portion can be spaced apart from the channel layer by the first portion, and the second portion is spaced apart from the gate electrode by the third portion. The second portion of the barrier layer can be configured to trap more charge, more readily recombine electrons and holes, or both as compared to each of the first and third portions of the barrier layer. The HEMT can have a VTH of at least 2 V and a subthreshold slope of at most 50 mV/decade of IDS.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: October 6, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Arno Stockman, Samir Mouhoubi, Abhishek Banerjee
  • Patent number: 10784847
    Abstract: A duty cycle correction circuit includes a duty cycle adjuster that is configured to receive first and second differential input signals having first and second duty cycles, respectively, that are distorted with respect to a reference duty cycle. The duty cycle adjuster is further configured to iteratively adjust the first and second duty cycles to generate first and second differential output signals having third and fourth duty cycles that are within a predefined range of the reference duty cycle, respectively. During each iteration, the duty cycle adjuster adjusts the first and second duty cycles based on correction bits that are generated based on a duty cycle detection signal that indicates whether the third duty cycle is greater than or less than the fourth duty cycle, and a lock signal that is activated when the duty cycle detection signal toggles from one logic state to another.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 22, 2020
    Assignee: NXP B.V.
    Inventors: Prakhar Tandon, Shivesh Kumar Dubey
  • Patent number: 10763846
    Abstract: An analog switch circuit is provided. The circuit includes a branch coupled between an input terminal and an output terminal. The branch is configured to transfer an input signal at the input terminal to the output terminal when a control signal is at a first state. A transistor in the branch includes a current electrode coupled at the input terminal and is configured for receiving the input signal having a voltage exceeding a voltage rating of the transistor. A level shifter includes an output coupled to a control electrode of the transistor and is configured to provide a first voltage sufficient to cause the transistor to be conductive without exceeding the voltage rating of the first transistor when the control signal is at the first state. A voltage generator is coupled to the level shifter and is configured to generate the first voltage based on the input signal.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 1, 2020
    Assignee: NXP USA, Inc.
    Inventors: Marcos Mauricio Pelicia, Ivan Carlos Ribeiro do Nascimento, Bruno Bastos Cardoso
  • Patent number: 10263610
    Abstract: The present invention provides a control method and a control circuit for a switch circuit and a corresponding switch circuit device. The control circuit comprises: an acquiring module, configured to acquire first time; a comparing module, connected with the acquiring module and configured to compare first time with first fixed time; and an adjusting module, connected with the comparing module. The adjusting module adjusts a cycle of a turn-on signal of a first switch transistor to second fixed time when the first time is less than the first fixed time. The adjusting module adjusts the sum of second time and the first fixed time to the second fixed time to achieve spread spectrum when the first time is more than the first fixed time. The control circuit for the switch circuit provided by the present invention is used for controlling the switch circuit for spread spectrum.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: April 16, 2019
    Assignee: JOULWATT TECHNOLOGY (HANGZHOU) CO., LTD.
    Inventors: Pitleong Wong, Siopang Chan, Feng Xu, Yuancheng Ren, Xunwei Zhou
  • Patent number: 10243554
    Abstract: According to a first aspect of the present disclosure, a power switching circuit is provided, comprising: a bandgap reference circuit configured to receive an input voltage and to generate a reference voltage in response to receiving said input voltage; a supply selection circuit configured to receive at least two supply voltages, to select the highest voltage of said supply voltages and to provide said highest voltage to the bandgap reference circuit. According to a second aspect of the present disclosure, a corresponding method of operating a power switching circuit is conceived.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: March 26, 2019
    Assignee: NXP B.V.
    Inventors: Guru Rachupalli, Venkata Satya Sai Evani, Jaydeep Dalwadi
  • Patent number: 10218348
    Abstract: A control circuit includes an inverter circuit including a high-side MOSFET and a low-side MOSFET connected to form a totem-pole, a first gate driver configured to switch the low-side MOSFET, a second gate driver configured to switch the high-side MOSFET, a bootstrap circuit configured to supply a voltage to the second gate driver, and a detection section configured to issue an anomaly signal when a current larger than a predetermined value flows in the inverter circuit. In response to the issuing of the anomaly signal, the low-side MOSFET is turned off, and the high-side MOSFET is turned off. After that, in a state in which a freewheeling current is flowing through the low-side MOSFET, the low-side MOSFET is turned on to prevent a bootstrap capacitor of the bootstrap circuit from being overcharged.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: February 26, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinji Sakai, Hisashi Oda
  • Patent number: 10169722
    Abstract: A cascading selective microwave isolator (cascade) includes a set of Josephson devices, each Josephson device in the set having a corresponding operating bandwidth of microwave frequencies. Different operating bandwidths have different corresponding center frequencies. A series coupling is formed between first Josephson device from the set and an nth Josephson device from the set. The series coupling causes the first Josephson device to isolate a signal at a first frequency from a frequency multiplexed microwave signal (multiplexed signal) in a first signal flow direction through the series coupling and the nth Josephson device to isolate a signal of an nth frequency in a second signal flow direction through the series, where the second signal flow direction is opposite of the first signal flow direction.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Baleegh Abdo
  • Patent number: 10164607
    Abstract: Certain aspects of the present disclosure are generally directed to an integrated circuit device. The integrated circuit device generally includes a capacitive element, a first switch having a first terminal coupled to a first terminal of a capacitive element, and a second switch coupled between the first terminal and a second terminal of the capacitive element in the integrated circuit device.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: December 25, 2018
    Assignee: SnapTrack, Inc.
    Inventor: Edgar Schmidhammer
  • Patent number: 8022752
    Abstract: A voltage reference circuit and method for generating a reference voltage using the circuit uses a comparison of the voltages on first and second nodes of a diode resistor network to produce a comparison signal, which is then used to increase the voltage on an output of a charge pump to generate the reference voltage.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: September 20, 2011
    Assignee: NXP B.V.
    Inventors: Marcel J. M. Pelgrom, Hendricus J. M. Veendrick, Victor Zieren
  • Patent number: 8022739
    Abstract: A charge pump circuit and a method of compensating current mismatch in a charge pump circuit. The charge pump circuit comprises a core charge pump circuit; a replica charge pump circuit for sensing a current mismatch in the core charge pump circuit and for converting the sensed current mismatch into a voltage signal V_ctrl; wherein V-ctrl is utilized for compensating the current mismatch in the core charge pump circuit.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: September 20, 2011
    Assignee: Agency for Science, Technology and Research
    Inventor: Dan Lei Yan
  • Patent number: 8019284
    Abstract: Methods and systems for blanking a transmission signal to prevent blockage by a recurring obstruction, such as a plurality of helicopter rotor blades, are provided. An obstruction that may block a communication line of sight path is monitored. It is determined when the obstruction is expected to block transmission of a transmitted signal along the communication line of sight path based on monitoring when the obstruction blocks the communication line of sight path. A transmission blanking signal is generated, where the transmission blanking signal is configured to selectively stop transmission of the transmitted signal along the communication line of sight path when the obstruction is expected to block the communication line of sight path.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: September 13, 2011
    Assignee: The Boeing Company
    Inventor: Anthony D. Monk
  • Patent number: 8018270
    Abstract: A charge pump circuit includes a first plurality of capacitors, and a first precharge circuit. The first plurality of capacitors are connected in parallel to each other. The first plurality of capacitors receive clock signals to perform sequentially pumping operations which generate a first higher voltage from a power voltage supplied. The first precharge circuit precharges a predetermined number of capacitors in the first plurality of capacitors at the power voltage. The predetermined number is greater than one.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: September 13, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Tatsuya Matano
  • Patent number: 8013667
    Abstract: A plurality of capacitors each of which has a first and a second electrode. A plurality of first switches is connected between the first electrodes of the plurality of capacitors and a first power supply. A plurality of second switches is connected between the second electrodes of the plurality of capacitors and a second power supply. A plurality of resistances each of which is connected between the first electrode of one of the plurality of capacitors and the second electrode of another capacitor and which connect the plurality of capacitors in series, a voltage for driving an actuator being output from the last stage of the plurality of capacitors connected in series.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: September 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tamio Ikehashi
  • Patent number: 8013662
    Abstract: An internal voltage generating apparatus includes: a voltage detector that detects the level of the internal voltage and outputs a fixed level detection signal and a variable level detection signal. An oscillation controller generates an oscillation enable signal according to whether the fixed level detection signal and the variable level detection signal are enabled. An internal voltage generator generates the internal voltage in response to the oscillation enable signal.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: September 6, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Gyo-Soo Chu
  • Patent number: 8013670
    Abstract: The present invention discloses a method, apparatus and system for obtaining the tuning capacitance of a Gm-C filter. The method includes: integrating a simulated capacitor within a given time via a current, where the simulated capacitor simulates the capacitor of the Gm-C filter which is set to an even capacitor array; and comparing the integral voltage obtained by the integration with the reference voltage, finding a simulated capacitance that makes the integral voltage equal to the reference voltage via gradual approaching by adjusting a control code, and determining the simulated capacitance as the tuning capacitance. The present invention improves the performance of a Gm-C filter without affecting the performance of the Gm-C filter.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: September 6, 2011
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Xiaosheng Zhu