Patents Examined by Jeffrey S. Zweizig
  • Patent number: 12388430
    Abstract: A programmable delay-line circuit is provided that includes a single ring oscillator that is calibrated continuously by a calibration logic circuit. A clock edge sampler samples an input clock responsive to a plurality of oscillator output signals from the ring oscillator to form a corresponding plurality of data output signals. A clock edge voter processes the data output signals to identify a first one of the oscillator output signals that samples an edge transition of the input clock. Based upon a desired delay, a decoder selects for a second one of the oscillator output signals to produce an output clock signal.
    Type: Grant
    Filed: February 13, 2024
    Date of Patent: August 12, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Wenjing Yin, Xu Zhang, Qingjin Du
  • Patent number: 12381474
    Abstract: Voltage generators with relatively low clock feedthrough are disclosed. A voltage generator can include a charge pump with a first set of two switches arranged between two voltages, a second set of two switches arranged between one of the two voltages and an output node, and a fly capacitor connected to the first and second sets of two switches. The voltage generator can include a clock generation circuit to provide clock signals such that the two switches of the first set transition state and the two switches of the second set transition state at different times. In certain embodiments, the charge pump includes a p-type fly capacitor connected to an output node by way of an n-type transistor. In some embodiments, a level shifter can generate a level shifted clock signal for the charge pump and includes cross coupled transistors to receive a regulated voltage provided to the voltage generator.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: August 5, 2025
    Assignee: Skyworks Solutions, Inc.
    Inventors: Jingfeng Gong, William Frede, Yeung Bun Choi
  • Patent number: 12372997
    Abstract: A processing device comprises: operation circuits that operate based on a clock signal supplied from a clock generation circuit; a distribution circuit that branches the clock signal and outputs branched clock signals to the operation circuits; and a detection circuit that compares outputs of the operation circuits and detects an error. At least one of the operation circuits is coupled to the distribution circuit via at least one conversion circuit that converts the clock signal into a clock signal capable of detecting an abnormality in the clock signal when an abnormality occurs in the clock signal.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: July 29, 2025
    Assignee: HITACHI INFORMATION AND TELECOMMUNICATION ENGINEERING, LTD.
    Inventors: Kenichi Sugita, Hideyuki Oguri, Takao Yamauchi, Hiroki Mizosoe
  • Patent number: 12368435
    Abstract: A control unit of a gate drive circuit applies, between a gate and a source of a switching element, a first voltage so as to turn on the switching element. After transference of drain current of the switching element, the control unit interrupts the first voltage and applies, between the gate and the source of the switching element, a second voltage that is lower than the first voltage and that is higher than a mirror voltage of the switching element. When no short-circuit current is flowing to the switching element, the control unit interrupts the second voltage and applies, between the gate and the source of the switching element, a third voltage higher than the second voltage.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: July 22, 2025
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuji Nemoto, Kohei Onda, Takayoshi Miki, Shota Morisaki
  • Patent number: 12368377
    Abstract: The present disclosure relates to a multi-voltage driving control method, apparatus, and device, and a computer-readable storage medium. The multi-voltage driving control method includes the following steps: obtaining a voltage sample of a mains supply, and determining a voltage region corresponding to the voltage sample; determining a driving circuit corresponding to the voltage region according to the voltage region and a default working voltage region; and controlling an electrical appliance to operate by the driving circuit. According to the multi-voltage driving control method provided by the present disclosure, a working voltage range of a mains supply is determined by detecting the mains supply in an electricity use environment; a working state of a circuit is dynamically adjusted according to a change of an input voltage of an electrical appliance, thereby achieving stable work of the electrical appliance in a multi-voltage environment.
    Type: Grant
    Filed: December 4, 2024
    Date of Patent: July 22, 2025
    Assignee: SHENZHEN INTELTRON INTELLIGENT SCIENCE & TECHNOLOGY CO., LTD.
    Inventor: Yangsheng Dong
  • Patent number: 12362731
    Abstract: This disclosure relates to a system for mitigating distortion in a signal, including a first calculation circuit configured to determine a bit-cell population available to be activated of a plurality of bit-cells based on a signal strength of an input signal, a second calculation circuit configured to determine a number of bit-cells to be activated based on the signal strength of the input signal, the number of bit-cells to be activated being less than or equal to the bit-cell population, a variable-width dynamic element matching network (“variable DEM”) configured to activate a first subset of bit-cells of the bit-cell population based on the number of bit-cells to be activated, and one or more fixed-width dynamic element matching networks (“fixed DEMs”) configured to activate a second subset of bit-cells of the bit-cell population based on the number of bit-cells to be activated.
    Type: Grant
    Filed: October 10, 2023
    Date of Patent: July 15, 2025
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Mark R. Peting
  • Patent number: 12361979
    Abstract: Techniques for an on-memory die voltage regulator is disclosed. In the illustrative embodiment, a voltage regulator on a memory die is enabled upon receipt of a memory operation. The illustrative voltage regulator includes an analog controller that controls a shunt current based on a current output voltage of the voltage regulator. The illustrative voltage regulator also includes a digital controller that controls several switches based on the input voltage that control an effective resistance of part of the voltage regulator.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: July 15, 2025
    Assignee: Intel Corporation
    Inventors: Veeresh Garag, Bharat V. Chauhan
  • Patent number: 12348228
    Abstract: A bipolar high voltage bipolar pulsing power supply is disclosed that can produce high voltage bipolar pulses with a positive high voltage pulse greater than about 2 kV followed by a negative high voltage pulse less than about ?2 kV with a positive to negative dwell period between the positive high voltage pulse and the negative high voltage pulse. A high voltage bipolar pulsing power supply, for example, can reproduce high voltage pulses with a pulse repetition rate greater than about 10 kHz.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: July 1, 2025
    Assignee: EHT Ventures LLC
    Inventors: Alex Henson, Kevin Muggli, Timothy Ziemba, Kenneth Miller
  • Patent number: 12341426
    Abstract: A semiconductor device includes: a storage circuit configured to be connected to a regulator circuit having characteristics to be identified using one or more values and store values identifying characteristics of the regulator circuit; and an electronic fuse controller including an input configured to be connected to an electronic fuse circuit including one or more electronic fuses, an output configured to be connected to the storage circuit, a reading control circuit, and a characteristic control circuit, in which the reading control circuit includes a reading circuit configured to read values from at least part of the electronic fuses through the input in a reading period, and the characteristic control circuit is configured to generate identification data configured to identify the characteristics based on a signal from the reading circuit and supply the identification data to the storage circuit through the output in an identifying period different from the reading period.
    Type: Grant
    Filed: September 18, 2023
    Date of Patent: June 24, 2025
    Assignee: LAPIS Technology Co., Ltd.
    Inventors: Ryuu Soga, Tomoyuki Maeda
  • Patent number: 12334920
    Abstract: A level shifter includes a level shifting circuit and a voltage tracking circuit. The level shifting circuit receives an input signal through an input terminal and converts the input signal from a first power domain to a second power domain to generate an output signal at an output terminal. The voltage tracking circuit is coupled to first and second voltage terminals, and tracks one with a lower level among voltages of the first and second voltage terminals to generate a control voltage. The level shifting circuit includes first and second N-type transistors. The first N-type transistor has a gate coupled to the input terminal, a drain coupled to a first node, and a source coupled to a ground. The second N-type transistor has a gate receiving the control voltage, a drain coupled to the output terminal at a second node, and a source coupled to the input terminal.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: June 17, 2025
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jung-Tsun Chuang, Shao-Chang Huang, Li-Fan Chen, Chun-Chih Chen, Gong-Kai Lin, Chien-Wei Wang
  • Patent number: 12334925
    Abstract: Systems, methods, and devices are described herein for generating a pulse width modulation (PWM) signal having a specific duty cycle. In one embodiment, the system includes a square wave generator and a logic device. The square wave generator is configured to delay a input square wave signal to generate a plurality of square wave signals. The logic device is configured to perform a logic operation to two of square wave signals of the plurality of square wave signals, which in turn generates the PWM signal having a duty cycle corresponding to the two square wave signals.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-An Lai, Chan-Hong Chern, Cheng-Hsiang Hsieh
  • Patent number: 12323142
    Abstract: At least one integrated power management cell of an IC includes a first cell, which is a 4-height cell, that includes a first continuous n-well, a first power interconnect coupled to a first voltage source associated with a first voltage domain and to the first continuous n-well, a second continuous n-well, a second power interconnect coupled to a second voltage source associated with a second voltage domain and to the second continuous n-well, a first subset of a first voltage level shifter associated with the first voltage domain and coupled to the first power interconnect, and a second subset of the first voltage level shifter associated with the second voltage domain and coupled to the second power interconnect.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: June 3, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Ramaprasath Vilangudipitchai, Venkat Narayanan, Giby Samson, Venugopal Boynapalli
  • Patent number: 12323136
    Abstract: A control device includes a triac and a first diode that is series-connected between the triac and a first terminal of the device that is configured to be connected to a cathode gate of a thyristor. A second terminal of the control device is configured to be connected to an anode of the thyristor. The triac has a gate connected to a third terminal of the device that is configured to receive a control signal. The thyristor is a component part of one or more of a rectifying bridge circuit, an in-rush current limiting circuit or a solid-state relay circuit.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: June 3, 2025
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Romain Pichon, Yannick Hague
  • Patent number: 12323042
    Abstract: A control method improves the efficiency profile of a power supply across a wide range of output loading. The method includes obtaining a measure of output power for a power supply, which includes one or more output modules and an auxiliary power supply. The method determines whether a maximum power rating of the auxiliary power supply is sufficient to provide the measure of output power. Responsive to a determination that the maximum power rating of the auxiliary power supply is sufficient to provide the measure of output power, the controller of the power supply directs the auxiliary power supply to provide the output power.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: June 3, 2025
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Xiqun Zhu, Sung Kee Baek, Joel Goergen, Doug Paul Arduini, Ruqi Li
  • Patent number: 12316210
    Abstract: Switch controller circuit (10) for controlling switching in a topology (1) having a first switch (4), a second switch (5), and a switching node (6) coupled therebetween. A driver arrangement (101,104,105) controls the first and second switches (4,5) to alternately open and close, wherein a deadtime period is applied between the opening of one switch (4) and the closing of the other switch (5) in use. A voltage sensor (106) connected to the switching node (6) provides feedback based on a sensed voltage as it transitions between high and low voltage states and sets a length of the deadtime period based on a measured first time period and a multiplier coefficient. The first time period is measured from a time of opening of one of the switches to a time when the sensed voltage transitions through a threshold set between the high and low voltage states.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: May 27, 2025
    Assignee: TDK-Lambda UK Limited
    Inventors: Leonard Dobos, Anthony New
  • Patent number: 12301107
    Abstract: Methods and systems of powering a radio that can be mounted on a tower of a wireless communication system are provided in which a direct current (“DC”) voltage is provided to the radio over a power cable from a power supply configured to change the direct current (DC) output from the power supply based on a measured current level. The power supply is configured to change the DC voltage from a first voltage level to a second voltage level in response to the measured current being greater than or equal to a first threshold value.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: May 13, 2025
    Assignee: Outdoor Wireless Networks LLC
    Inventor: John T. Hanley
  • Patent number: 12294358
    Abstract: A resettable digital stage operates when a supply voltage is higher than a threshold. A non-volatile memory stores a digital code read by a reading stage. A main power-on reset circuit generates a main reset signal controlling reset of the reading stage. A resettable volatile memory coupled to the reading stage stores a default value when reset. An auxiliary power-on reset circuit generates an auxiliary reset signal controlling reset of the volatile memory. Upon deactivation of the reset, the reading stage loads the digital code into the volatile memory. The main power-on reset circuit functions in a non-trimmed configuration response to the stored default value and in a trimmed configuration responsive to the stored digital code. The main power-on reset circuit has first and second operative thresholds which respectively fall within a first and second non-trimmed voltage range or within a first and second trimmed voltage range.
    Type: Grant
    Filed: January 10, 2024
    Date of Patent: May 6, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Riccardo Condorelli, Antonino Mondello, Michele Alessandro Carrano, Daniele Mangano, Fabien Laplace, Luc Garcia, Michel Cuenca
  • Patent number: 12289039
    Abstract: A high-frequency power supply system according to the present disclosure includes a first power supply, a second power supply, a first matcher, and a second matcher. The second power supply performs pulse modulation of repeating an ON operation of outputting a second forward wave voltage and an OFF operation of not outputting the second forward wave voltage. The first power supply performs frequency modulation control in a second power supply ON period, and performs frequency offset control of outputting a forward wave voltage having a fundamental frequency obtained by adding an offset frequency to a fundamental frequency in a second power supply OFF period.
    Type: Grant
    Filed: December 27, 2023
    Date of Patent: April 29, 2025
    Assignee: DAIHEN Corporation
    Inventors: Yuya Ueno, Yuichi Hasegawa
  • Patent number: 12277002
    Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: April 15, 2025
    Assignee: Astera Labs, Inc.
    Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
  • Patent number: 12273102
    Abstract: This application discloses a system for turning off power consumption of an auxiliary startup circuit. An oscillator generates a switch control signal based on a reference current output by a circuit to be started up to generate a working clock of a switch control signal generation circuit after the circuit to be started up works normally. After fixed clock signal counting, the switch control signal generation circuit outputs a switch control signal to control power consumption of normally open current of the auxiliary startup circuit to be turned off. At the same time, the switch control signal generation circuit stops counting the clock. This application can assist the circuit to be started up having a “degeneracy” bias point to power on normally, and can also turn off the power consumption of the auxiliary startup circuit after the circuit to be started up is powered on.
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: April 8, 2025
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Xiaofeng Su, Yifei Qian, Zhili Wang