Abstract: A resettable digital stage operates when a supply voltage is higher than a threshold. A non-volatile memory stores a digital code read by a reading stage. A main power-on reset circuit generates a main reset signal controlling reset of the reading stage. A resettable volatile memory coupled to the reading stage stores a default value when reset. An auxiliary power-on reset circuit generates an auxiliary reset signal controlling reset of the volatile memory. Upon deactivation of the reset, the reading stage loads the digital code into the volatile memory. The main power-on reset circuit functions in a non-trimmed configuration response to the stored default value and in a trimmed configuration responsive to the stored digital code. The main power-on reset circuit has first and second operative thresholds which respectively fall within a first and second non-trimmed voltage range or within a first and second trimmed voltage range.

Abstract: A high-frequency power supply system according to the present disclosure includes a first power supply, a second power supply, a first matcher, and a second matcher. The second power supply performs pulse modulation of repeating an ON operation of outputting a second forward wave voltage and an OFF operation of not outputting the second forward wave voltage. The first power supply performs frequency modulation control in a second power supply ON period, and performs frequency offset control of outputting a forward wave voltage having a fundamental frequency obtained by adding an offset frequency to a fundamental frequency in a second power supply OFF period.

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Abstract: This application discloses a system for turning off power consumption of an auxiliary startup circuit. An oscillator generates a switch control signal based on a reference current output by a circuit to be started up to generate a working clock of a switch control signal generation circuit after the circuit to be started up works normally. After fixed clock signal counting, the switch control signal generation circuit outputs a switch control signal to control power consumption of normally open current of the auxiliary startup circuit to be turned off. At the same time, the switch control signal generation circuit stops counting the clock. This application can assist the circuit to be started up having a “degeneracy” bias point to power on normally, and can also turn off the power consumption of the auxiliary startup circuit after the circuit to be started up is powered on.

Abstract: A voltage generation circuit includes a booster circuit, a control buffer circuit, and a driving buffer circuit. The booster circuit includes a capacitance element and a transistor. The booster circuit generates a higher first voltage than the power source voltage, and the control buffer circuit controls the transistor by using a third voltage that is lower than the first voltage and is higher than a ground voltage. Alternatively, the booster circuit generates a lower second voltage than the ground voltage, and the control buffer circuit controls the transistor by using a fourth voltage that is higher than the second voltage and is lower than or equal to the ground voltage.

Abstract: An apparatus comprises: a first power source to generate first voltages; a power switch to supply the first voltages to a load as load voltages or not supply the first voltages to the load; first sensors to sense first sensed voltages based on the first voltages, and load sensors to sense the load voltages to produce sensed load voltages; and a controller to: upon detecting a failure of the first sensors, identify a faulty sensed voltage of the first sensed voltages caused by the failure based on at least the first sensed voltages and whether the power switch supplies or does not supply the first voltages to the load; compute a reconstructed sensed voltage to replace the faulty sensed voltage based on healthy sensed voltages of the first sensed voltages that are not faulty; and monitor the healthy sensed voltages and the reconstructed sensed voltage.

Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.

Abstract: A semiconductor device includes a switching circuit that switches between conducting state and disconnected state. The switching circuit includes first and second switching elements electrically connected in parallel. The first switching element is an IGBT, and the second switching element is a MOSFET. When a current flowing in the switching circuit is less than a first current value, the second switching element has a lower voltage than the first switching element. When the current flowing in the switching circuit is not less than a second current value and not greater than a third current value, the threshold voltage of the second switching element ranges from ?1.0 V to +0.4 V relative to the threshold voltage of the first switching element. The third current value is not greater than the rated current of the switching circuit. The first current value is less than the third current value.

Abstract: An embodiment of the present disclosure provides a zero standby power system, comprising a power supply device comprising a plurality of power stages and a zero standby power device configured to receive an on/off signal and to control connections respectively to the plurality of power stages based on the received on/off signal, wherein the zero standby power device may comprise an on/off controller configured to be maintained to be in an operation state and to receive an on/off signal at an arbitrary time point.

Abstract: A circuit board includes: a first plurality of integrated circuit (IC) chips, a second plurality of IC chips that is distinct from the first plurality of IC chips, a first power rail configured to provide power to the first plurality of IC chips, and a second power rail configured to provide power to the second plurality of IC chips. A controller is configured to receive sensor data from the first plurality of IC chips and the second plurality of IC chips and independently determine, based on the sensor data, a first power supply voltage for the first power rail and a second power supply voltage for the second power rail. The first power supply voltage and the second power supply voltage are different from one another. A power supply is configured to provide the first and second power supply voltages to the first and second power rails.

Abstract: Circuits and methods for providing a “bootstrap” power supply for level-shifter/driver (LS/D) circuits in a FET-based power converter. In a first embodiment, linear regulators and a bootstrap capacitor provide a bootstrap power supply for level-shifter/driver circuits in each tier of a multi-level FET-based power converter. In a second embodiment, floating charge circuits and bootstrap capacitors provide an improved bootstrap power supply for level-shifter and driver circuits in each tier of a multi-level FET-based power converter. More particularly, a floating charge circuit configured to be coupled to an associated bootstrap capacitor includes a first sub-circuit configured to pre-charge the associated bootstrap capacitor when coupled and a second sub-circuit configured to transfer charge between the bootstrap capacitor and a bootstrap capacitor coupled to an adjacent floating charge circuit.

Abstract: A digital Power on Reset (POR) circuit includes N counters; N comparators each connected to an output of a corresponding counter of the N counters to compare with a corresponding specific value, N is an integer greater than or equal to 1; and a comparison block connected to an output of each of the N comparators and configured to output a reset signal based on the output of each of the N comparators. The digital POR circuit utilizes a complete digital design, enabling efficient integration with a processing circuit. The digital POR circuit can utilize the same libraries, cells, etc. as other digital components in the processing circuit, and can be tested with other digital components in the processing circuit.

Abstract: Disclosed in the present invention are a charge pump circuit, a chip, and a communication terminal. The charge pump circuit comprises a phase clock generation module, an acceleration response control module, and a plurality of sub charge pump modules. By generating a plurality of clock signals with a fixed phase difference by means of the phase clock generation module, correspondingly controlling the plurality of sub charge pump modules to generate output voltages, and by means of the acceleration response control module, measuring the output voltage of each sub charge pump module, and separately outputting a logic signal to the phase clock generation module and each sub charge pump module, the frequency of the clock signals outputted by the phase clock generation module is changed, and the charge and discharge time of a capacitor in each sub charge pump module is reduced.

Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.

Abstract: A transversal radio frequency filter circuit having a low noise amplifier connected along an input signal path, a first power divider connected between the low noise amplifier and four single taps, and an output path connected to the outputs of each of the four single taps. Each of the four single taps having a coefficient control mechanism, a polarity selection mechanism, and a time delay element. The coefficient control mechanism can include a wideband digital step attenuator configured to support high control range of the coefficient. Additionally, the circuit can include a second power divider connected between the outputs of each of the four single taps and the output path. The circuit can further include a field-programmable gate array configured to control coefficient control mechanisms, the polarity selection mechanisms, and the time delay elements (when they are variable time delay elements).

Abstract: An electric circuit includes a first power-supply line, a second power-supply line, a ground line, a first circuit, a second circuit, an RC series circuit, a capacitor, and a noise filter. The first circuit is configured to be electrically connected to the first power-supply line via a first power-supply terminal and electrically connected to the ground line via a first ground terminal. The second circuit is configured to be electrically connected to the second power-supply line via a second power-supply terminal and electrically connected to the ground line via a second ground terminal. The RC series circuit is disposed between the first power-supply terminal and the first ground terminal. The capacitor is disposed between the second power-supply terminal and the second ground terminal. The noise filter is disposed between the first power-supply line and the second power-supply line.

Abstract: A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.

Abstract: A half-bridge circuit driving chip includes a control module, a level shift unit, a programming module, and a driving unit. The control module is configured to receive an enabling signal and an input signal, and output a set signal and a reset signal. The level shift unit is configured to receive the set signal and the reset signal, and output a relative set signal and a relative reset signal. When the enabling signal is at a low level, the half-bridge circuit driving chip is in a programming mode, and the programming module performs decoding according to the relative set signal and the relative reset signal, and outputs a circuit parameter. When the enabling signal is at a high level, the half-bridge circuit driving chip is in a working mode, and the driving unit generates an output signal according to the relative set signal and the relative reset signal.

Abstract: A gate drive circuit is used in a dynamic characteristic test on a power semiconductor, the gate drive circuit includes a voltage source configured to change a gate voltage of a gate of the power semiconductor, a plurality of resistance setting circuits connected in parallel with the voltage source and the gate, and a switching circuit connecting at least one resistance setting circuit of the resistance setting circuits to the voltage source and the gate.

Abstract: In one example, a system comprises a plurality of charge pump units connected in parallel to receive an input voltage and to generate an output voltage greater than the input voltage and a pumping controller to provide a pumping signal to a first charge pump unit of the plurality of charge pump units and to provide sequentially delayed versions of the pumping signal to the other charge pump units of the plurality of charge pump units.