Abstract: A method and system for providing an output voltage greater than a voltage provided by a voltage supply in a semiconductor device are disclosed. The method and system include providing a plurality of clock signals, providing a first stage and providing a second stage. The first stage includes at least a first pumping node, a pumping capacitor and a device coupled with the pumping node, and an auxiliary capacitor pair for providing an undershoot for the device for value(s) of the clock. The auxiliary and pumping capacitors receive a first portion of the clock signals. The second stage includes at least a second pumping node. The first and second portions of the clock signals are provided to the first and second stages, respectively. The first stage and the second stage are configured to alternately charge and fully discharge based on the clock signals.

Abstract: The invention relates to a method for obtaining temperature values from at least two thermal sensors arranged on resources within a three-dimensional die structure determining at least a partial three-dimensional temperature distribution for said die structure and controlling activity of said resources of said dies in response to said three-dimensional temperature distribution.

Abstract: A semiconductor device is provided which includes: a first semiconductor integrated circuit; a ground line and a power supply line trough which electric power is supplied to the first semiconductor integrated circuit; and a variable impedance component which is connected between the ground line and the power supply line.

Abstract: In a quantum computing circuit forming a superconductive loop including a plurality of Josephson junctions, first and second superconductive magnetic flux quantum bit element (101, 102) are biased at a half-quantum magnetic flux, and have mutually different characteristic frequencies. A coupling superconductive magnetic flux quantum bit clement element (103) is located between the first and second superconductive magnetic flux quantum bit elements (101, 102) to perform parametric variable control between the element (101, 102) by supplying a microwave magnetic field pulse which is equal to the frequency difference between the elements (101, 102).

Abstract: A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.

Abstract: A circuit, method for regulation, and use thereof is provided, whereby the circuit can include a charge pump that is connected to a supply voltage terminal in order to produce a pump voltage from a supply voltage, and includes a control circuit whose inputs are connected to the output of the charge pump and to the supply voltage terminal in order to sense a difference between the pump voltage and the supply voltage as a controlled variable. The circuit is designed to compare the controlled variable to a reference variable, and output is connected to a control input of the charge pump in order to control the charge pump as a function of the comparison.

Abstract: A voltage detector device is disclosed that includes a coarse-range voltage detector and a fine-range voltage detector. The fine-range voltage detector is configured to remain inactive, so that it consumes a relatively small amount of power, while a monitored voltage is outside a first specified range. In response to determining that the monitored voltage is within the first specified range, the coarse-range voltage detector activates the fine-range voltage detector so that it can monitor the voltage. In response to the fine-voltage monitor determining the voltage falls within a second specified range, the fine-range voltage detector provides a signal to a functional module of an electronic device so that the functional module can provide a defined response, such as executing an interrupt routine.

Abstract: A step-down circuit is connected between a power supply node for supplying a supply voltage and an internal power supply line for supplying a power to the object circuit and steps-down the supply voltage, and supplies the stepped-down voltage to the object circuit through the internal power supply line. The step-down circuit includes a comparison circuit that compares a reference voltage with the voltage of the internal power supply line, and a driver that adjusts a current flowing between the internal power supply line and the power supply node according to the comparison result of the comparison circuit. The activity level of the driver is controlled so as to rise in a predetermined rising period synchronously with an activated operation of the object circuit and to fall in a predetermined falling period that comes after the rising period.

Abstract: A semiconductor memory device includes a voltage detector configured to detect a voltage level of an external power supply voltage, a first core voltage generation driver configured to operate when the external power supply voltage is in a high level region and a second core voltage generation driver configured to operate when the external power supply voltage is in a low level region.

Abstract: A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).

Abstract: Between a control terminal (gate) of an output transistor of a source follower configuration and an output terminal to which a load is coupled, a depletion transistor having a relatively lower breakdown voltage (that is, smaller device-area) is provided as a shutdown transistor of the output transistor, to thereby control a conductive state/nonconductive state of the depletion transistor. There are provided: the output transistor of the source follower configuration coupled between a first power supply line and the output terminal; the load coupled between the output terminal and a second power supply line; the depletion transistor coupled between the gate of the output transistor and the output terminal; and a control circuit controlling the conductive state/nonconductive state of the depletion transistor by applying, between a gate and a source thereof, a voltage smaller than a voltage deference between a potential of the first power supply line and a potential of the second power supply line.

Abstract: In one embodiment, a circuit includes a first row of circuit blocks that are each connected to a supply directly and to ground via a first sleep transistor. A connection between the first circuit block and the first sleep transistor is a virtual ground node. The circuit includes a second row of circuit blocks that are each connected to ground directly and to the supply via a second sleep transistor. A connection between the second circuit block and the second sleep transistor is a virtual supply node. The circuit includes a transmission gate (TG) or pass transistor connecting the virtual ground nodes to the virtual supply nodes to enable charge recycling between circuit blocks in the first row and circuit blocks in the second row during transitions by the circuit from active mode to sleep mode, from sleep mode to active mode, or both.

Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Abstract: An internal voltage control apparatus capable of reducing current consumption and a semiconductor memory device using the same includes an enable signal generating unit for generating an enable signal in response to an active signal and an internal voltage driving unit driven by the active signal and the enable signal, wherein the internal voltage driving unit drives an internal voltage by comparing the internal voltage and a reference voltage and then generating first and second driving signals, and wherein the enable signal generating unit receives the second driving signal and then determines enablement of the enable signal.

Abstract: A comparator component having a comparison circuit and bias generator circuit, with the bias generator circuit also having a same number of transistors connected in an identical configuration, as those contained in the comparison circuit to generate a comparison result based on the bias signal generated by the bias generator circuit. A transistor of the comparison circuit receiving the bias signal is connected to a corresponding transistor in the bias generator circuit, in a current mirror configuration. The same bias circuit may be shared by many comparison circuits of corresponding comparator components. The features can be extended to provide hysteresis.

Abstract: A pumping voltage detector includes a first division voltage generating unit for dividing a pumping voltage at a first division ratio to generate a first divided voltage, a second division voltage generating unit for dividing the pumping voltage at a second division ratio different from the first division ratio to generate a second divided voltage, and a detection signal generating unit for comparing one of the first and second divided voltages with a reference voltage to generate a pumping voltage detection signal.

Abstract: Provided is a reference current generating circuit capable of maintaining a constant output level regardless of a temperature variation by the use of a reference resistor having a constant resistance regardless of the temperature variation. The reference current generating circuit includes a reference voltage circuit supplying a reference voltage having a constant level regardless of a temperature variation, and a reference resistor circuit comprising a resistor having a positive temperature coefficient and a resistor having a negative temperature coefficient that are connected in series, the reference resistor circuit having a constant total resistance regardless of the temperature variation. Herein, a reference current having a constant level regardless of the temperature variation is generated by the reference voltage and the resistance of the reference resistor circuit.

Abstract: Core voltage generator including a comparison unit configured to compare a reference voltage with a feedback core voltage to output a difference between the reference voltage and the feedback core voltage, an amplification unit configured to output a core voltage by amplifying an external power supply voltage according to an output signal of the comparison unit and a mute unit configured to maintain a voltage level of an output terminal of the amplification unit at a ground voltage level when the output of the core voltage is interrupted.

Abstract: An integrated electronic device includes a sample and hold stage. The sample and hold stage has a sampling capacitor (C) for an input voltage at an input node (Vin), a first switch (S1) coupled between the input node (Vin) and the sampling capacitor (C) for connecting the input node (Vin) to the sampling capacitor (C). There is also a voltage follower with an input coupled to the sampling capacitor (C). The first switch (S1) includes a first MOS transistor (NM1) coupled between the input node (Vin) and the sampling capacitor (C). The first MOS transistor has a bulk. The sample and hold stage is adapted to selectively couple the bulk to a node having a voltage level (V3) which is equal or close to the voltage level at the input node of the voltage follower.

Abstract: This invention discloses charge pump apparati, where a charge pump apparatus, including a positive charge pump circuit and a negative charge pump circuit, providing multiple positive and negative voltages, comprises: a capacitor set shared by said positive charge pump circuit and said negative charge pump circuit; multiple electronic switches connected to said capacitor set and a plurality of voltage sources; multiple output capacitors connected to selected ones of said multiple electronic switches and one or more output terminals; and a non-overlapping time sequence that controls the on and off states of said multiple electronic switches; wherein under the control of said non-overlapping time sequence, corresponding electronic switches are turned on and off to control the output of the positive and negative voltages provided by said output capacitors to generate output voltages that are pre-determined multiples of the one or more input voltages.