Abstract: A power supply detection circuit biased by at least two power supply voltages for controlling a signal driver circuit. Upstream and downstream amplifiers, powered by upstream and downstream power supply voltages, respectively, process an original control signal to produce a differential signal via output signal electrodes. Capacitances coupling respective ones of the output signal electrodes to the downstream power supply voltage and the circuit reference potential discharge and charge respective ones of the output signal electrodes in relation to initial receptions of the upstream and downstream power supply voltages and original control signal, following which voltage clamp circuitry maintains such discharged and charged states pending reception of the original control signal in a predetermined state.

Abstract: An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages to provide the first output voltage to the first node. The first output voltage is maintained between the first and second reference voltages. The second driving circuit receives a feedback voltage from a second node voltage and generates a second output voltage based on third and fourth reference voltages to provide the second output voltage to the second node. The second output voltage is maintained between the third and fourth reference voltages, and the second output voltage of the second node is provided as an internal supply voltage. The resistive device is coupled between the first and second nodes.

Abstract: An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data path transfers the sense output signal, and latches the sense output signal to output the sense output signal to the first node. The third data path latches a signal of the first node, and transfers the signal of the first node to generate output data. Accordingly, the semiconductor memory device including the output circuit can operate at a relatively higher frequency using a pseudo-pipeline structured circuit, which combines a wave pipeline structure with a full pipeline structure.

Abstract: A trim circuit that is operable to adjust (trim) a digital or analog output of another electronic circuit, e.g., a regulator, comparator, signal processor, and the like. The novel trim circuit includes two fuses that can be separately “blown” or severed in such a way as to provide a relatively fixed “high” or “low” output signal that can be employed to adjust/trim the digital or analog output of another electronic circuit. A first fuse is coupled to a high potential of the trim circuit and the second fuse is coupled to a low potential of the trim circuit. If the second fuse is blown/cut, the trim circuit provides a relatively fixed high output signal. Conversely, if the first fuse is blown/cut, the trim circuit provides a relatively fixed low output signal. The fuses typically operate as relatively low impedance current shunts until they are severed/cut.

Abstract: A circuit generates a reference voltage that is independent of temperature. The circuit is built on a substrate according to a CMOS technology, and includes a first stage for generating a first current proportional to temperature and a second stage for generating a second current inversely proportional to temperature. These first and second currents are summed in a resistor connected to a voltage distinct from the ground of the first and second stages and formed by the voltage of the substrate on which the circuit is built.

Abstract: In general, in one aspect, the disclosure describes a programmable power gating circuit that includes a reference voltage generator to generate a reference voltage and a voltage selector, coupled between a voltage source and active circuitry, to gate application of the voltage source to the active circuitry and provide a certain voltage to the active circuitry when the active circuitry is in a reduced capacity mode. The certain voltage is based on the reference voltage.

Abstract: Example systems and methods for a charge pump are disclosed. A charge pump may comprise a pump capacitor configured to charge when electrically coupled to a sleep signal and discharge when electrically coupled to an output, a means for receiving an alternating signal which electrically couples a VDD signal or an output to the pump capacitor based on a state of the alternating signal, a means for receiving a complement of the alternating signal which electrically couples the sleep signal with the pump capacitor based on a state of the complement of the alternating signal, and a means to electrically couple the alternating signal and the complement of the alternating signal to a node based on the state of the alternating signal and the state of the complement of the alternating signal.

Abstract: A semiconductor integrated circuit according to the present invention comprises a circuit as a controlled object including an MOS transistor, wherein a control potential (at least one of a substrate potential and source potential) is to be controlled, a control signal generation circuit for generating a control signal with respect to the control potential based on an internal signal of the circuit as the controlled object, and a control potential control circuit for controlling the control potential (substrate potential/source potential) of the MOS transistor based on the control signal.

Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

Abstract: A semiconductor integrated circuit having a circuit block including a MOS transistor that includes a bias input terminal, a source, and a substrate, in which the bias voltage is applied to the MOS transistor at a position of at least one of the source and the substrate through the bias input terminal, a setting unit operable to set up applying timing and releasing timing at which the bias voltage is applied to and released from the MOS transistor, and a bias voltage-applying unit operable to apply the bias voltage to the MOS transistor at the applying timing and the releasing timing. In the semiconductor integrated circuit, the setting unit sets up, as the releasing timing, timing prior to activation timing by a predetermined time period. An operation-requesting signal, to be sent out to the circuit block by the setting unit, is activated at the moment of the activation timing.

Abstract: A trimmable voltage reference uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The threshold voltage of the flash cell can be programmed to affect the reference voltage.

Abstract: The present invention provides a Driver circuit having dynamically adjusting output current and limiting input current function. This present invention dynamically adjusts the output current provided by the driver unit to reduce this output current in real time. A protection circuit is also provided to limit the input current supplied to the driver unit. This present invention avoids overdriving the driver unit.

Abstract: A pulse detection circuit detects one different pulse within a string of similar pulses for a once per revolution index. The pulse detection circuit comprises a DC averaging means for generating a first threshold voltage from a raw signal. An average comparator receives the first threshold voltage and generates a first output voltage indicative of signal amplitude of the raw signal, as compared to the first threshold voltage. A zero comparator receives the raw signal, compares it to zero, and generates a second output voltage indicative of a pulse. The first and second output voltages are input to a logic sequence to generate a logic output when the one different pulse within the string of similar pulses is detected.