Abstract: A charge pump includes a level shifter and a charge exchange control switching circuit. The level shifter can enhance the levels of a first and second clock signals, and output a first and a second control signal corresponding to the enhanced signals. Based on the first and second control signals, the charge exchange control switching circuit amplifies an input voltage and generates a corresponding amplified output voltage.

Abstract: The pin number reduction circuit circuits and methodology of the present invention provide a higher pseudo power supply and a lower pseudo power supply for a digital functional section in mixed-signal IC, memory IC, and SOC including analog functional section and digital (or memory) functional section in order to reduce digital noise coupling. The circuit and methodology of the present invention basically includes resistors, capacitors, transistors, and amplifiers. It is noted that analog functional section is coupled between a positive power supply and a negative power supply, which are connected to two pins. One amplifier with a PMOS transistor and one resistor string provides a higher pseudo power supply, and the other amplifier with an NMOS transistor and the other resistor string provides a lower pseudo power supply so that a digital functional section is coupled between these pseudo power supplies.

Abstract: A voltage generator has a control circuit for controlling a dual-mode charge pump that has multiple control options provided by an optional pull down control signal and an optional stop control signal. The dual-mode charge pump is enabled by a high voltage enable control signal from a control circuit to provide a high-voltage output voltage level Vpp or a low-voltage output voltage level Vdd. A current sink transistor is coupled from the output of the dual-mode charge pump to a ground reference through a current sink control switch transistor that is turned on by the optional pull down control signal. A dual output op amp compares a fixed voltage reference to a voltage proportional to the output voltage of the charge pump. The op amp has a high voltage output signal terminal that turns on the current sink transistor and a low voltage output signal that is coupled to the control circuit.

Abstract: Provided is a charge pump circuit whose power efficiency is not reduced even when a threshold voltage of a transistor is increased by a substrate effect with an increase in the number of stages. A depletion transistor is used as an N-channel transistor included in an inverter of a high-voltage clock generating circuit. A P-channel enhancement transistor is used as a charge transfer device.

Abstract: A method and a device for regulating the threshold voltage of a transistor is disclosed. The device includes a circuit configured for modifying a voltage applied at a bulk connection of the transistor such that the threshold voltage of the transistor is substantially temperature-independent at least in a first temperature range. In one embodiment, the device includes a memory device, and the transistor is a transistor of a sense amplifier of the memory device.

Abstract: A device controls internal voltage. Increased reliability of a semiconductor memory device is obtained by increasing or decreasing a level of internal reference voltage according to change of the device. Fuse ROMs generate fuse signals having different levels according to a cutting condition of each fuse. A bit counter performs up/down counting operation in response to a count control signal after setting the fuse signals to initial values in response to a set signal and generates counter output signals which are higher or lower than the initial values by a counting number. A decoder decodes the counter output signals and activates one of switching signals. A reference voltage selector provides a trimming level of internal reference voltage in response to the switching signals and generating reference voltage.

Abstract: The internal voltage generator of a semiconductor integrated circuit includes at least one variable reference voltage generating unit that generates a base reference voltage increased or decreased according to the variation in temperature, at least one level shifting unit that transforms the base reference voltage outputted by the at least one variable reference voltage generating unit into at least one prescribed reference voltage for generating internal voltage and outputs the transformed reference voltage, and at least one internal voltage generating unit that generates an internal voltage by using the at least one reference voltage for generating internal voltage outputted by the at least one level shifting unit.

Abstract: Techniques for adaptively scaling voltage for a processing core are described. In one scheme, the logic speed and the wire speed for the processing core are characterized, e.g., using a ring oscillator having multiple signal paths composed of different circuit components. A target clock frequency for the processing core is determined, e.g., based on computational requirements for the core. A replicated critical path is formed based on the characterized logic speed and wire speed and the target clock frequency. This replicated critical path emulates the actual critical path in the processing core and may include different types of circuit components such as logic cells with different threshold voltages, dynamic cells, bit line cells, wires, drivers with different threshold voltages and/or fan-outs, and so on. The supply voltage for the processing core and the replicated critical path is adjusted such that both achieve the desired performance.

Abstract: A flash memory device applies a low read voltage at increased flash memory device temperatures. A high read voltage is applied when a supply voltage is high, thereby maintaining a stable threshold voltage margin of a programmed cell or an erased cell. As a result, the reliability of the flash memory cell is enhanced.

Abstract: An internal voltage generator supplies a stable internal voltage without increasing standby current. The internal voltage generator includes an internal voltage driver for supplying an internal voltage based on a control signal, a feedback circuit for supplying a feedback voltage having a voltage level proportional to the internal voltage, a control signal generating circuit for generating the control signal to control the internal voltage driver such that the feedback voltage is maintained at a desired reference voltage, an auxiliary driving circuit for additionally supplying the internal voltage in response to the control signal, and an auxiliary driving control circuit for activating the auxiliary driving circuit only when it is expected to dissipate a large amount of a current.

Abstract: A semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.

Abstract: To a frequency divider having a reset function, a second clock of a frequency N×Y times higher than that of a first clock is inputted. Upon receipt of a signal indicating that the stop of the input clock is detected by a start/stop detection circuit, the frequency divider having a reset function resets the dividing of a frequency. Then, upon receipt of a signal indicating that the resumption of the input clock is detected by the start/stop detection circuit, the frequency divider generates and inputs a third clock to a phase comparator by starting the dividing of a frequency.

Abstract: A constant ratio current source comprises a first current branch which includes a first transistor that conducts a current I1 from a first current input to a first node and a resistor R1 connected between the first node and a circuit common point, and a second current branch which includes a second transistor that conducts a current I2 from a second current input to a second node and a resistor R2 connected between the second node and the circuit common point. The current branches are arranged such that I2 varies with I1. A linear negative resistance circuit connected between the first and second nodes provides an apparent negative resistance that increases the differential output impedance at the first and second current inputs, such that the ratio of I2:I1 is maintained approximately constant for a varying differential voltage applied across the first and second current inputs.

Abstract: A digital temperature detection circuit for a semiconductor circuit comprises a digital temperature defection block and a data conversion block. The digital temperature detection block is adapted to detect an internal temperature of the semiconductor device and generate detection data having a data value that varies according to the detected internal temperature. The data conversion block is adapted to convert the detection data into standard data with a predetermined response interval using first and second sample data having respective data values that are determined by input from an external source.

Abstract: A circuit producing a reversed bandgap reference voltage circuit VRBG includes first and second resistors coupled as a voltage divider between ground and a first conductor, a base of a first transistor being coupled to the voltage divider to produce a first voltage VBE1(1+1/M) between the first conductor and ground, M being a ratio of the resistances of the first and second resistors. A third resistor is coupled between a base of the second transistor and ground to produce a second voltage VBE2+VRBGP between the second conductor and ground. First circuitry forces the collector current of the first transistor to be equal to the collector current of the second transistor, and second circuitry forces the first voltage VBE1(1+1/M) to be equal the second voltage VBE2+VRBGP. One of the first circuitry and second circuitry includes an operational amplifier coupled to effectuate the forcing.

Abstract: Systems and methods are discussed for using a floating-gate MOSFET as a programmable reference circuit. One example of the programmable reference circuit is a programmable voltage reference source, while a second example of a programmable reference circuit is a programmable reference current source. The programmable voltage reference source and/or the reference current source may be incorporated into several types of circuits, such as comparator circuits, current-mirror circuits, and converter circuits. Comparator circuits and current-mirror circuits are often incorporated into circuits such as converter circuits. Converter circuits include analog-to-digital converters and digital-to-analog converters.

Abstract: A modulator apparatus operating at a low supply voltage, configured for receiving an input-voltage signal in base band and supplying an output-voltage signal at a given modulation frequency under control of a signal generated by a local oscillator and comprising a transconductor stage that carries out a voltage-to-current conversion of said input-voltage signal. A voltage-to-current conversion module is coupled to a current-mirror module configured for mirroring a current in a Gilbert-cell stage, which supplies an output-voltage signal under the control of said signal generated by the local oscillator. The Gilbert-cell stage further comprises an output load for carrying out a current-to-voltage conversion and supplying the output-voltage signal. Said transconductor stage further comprises a differential feedback network configured for reproducing said input-voltage signal on a differential load included in said voltage-to-current conversion module.

Abstract: Dual edge modulated charge pumping circuit has an output terminal, a charge pumping conversion circuit, and a dual edge modulated control circuit. The charge pumping conversion circuit has a first capacitor, a second capacitor, and a switch combination circuit. The second capacitor is coupled between the output terminal and a ground potential. The dual edge modulated control circuit controls the switch combination circuit such that the charge pumping conversion circuit operates with a first phase, a second phase, a third phase, and a fourth phase. During the first phase, a first electrode of the first capacitor is floated. During the second phase, the first capacitor is coupled between the ground potential and an input voltage. During the third phase, the first capacitor is coupled between the input voltage and the output terminal. During the fourth phase, the first electrode of the first capacitor is floated.

Abstract: A system may include detection of a direction of transistor body current flow, and control of a regulator transistor to regulate a transistor body voltage based on the detected direction. In some aspects, a first regulator transistor is controlled if the direction of current flow is into a transistor body and a second regulator transistor is controlled if the direction of current flow is out of the transistor body.

Abstract: An exponential charge pump uses a number of identical or similar charging stages, each having a first and second capacitor. During a first clock phase, the first capacitor of each stage is charged by the second capacitor of the preceding stage, and, during a complementary second clock phase, the positive plate of the first capacitor of each stage is pushed to an increased voltage by the first capacitor of the preceding stage and charges the second capacitor of the next stage to the increased voltage at the same time. A similar mechanism occurs to the second capacitors in each stage, but with complementary timing. The increased voltage of the first capacitor of the last stage is pumped to an output capacitor during the second clock phase, and the increased voltage of the second capacitor of the last stage is pumped to an output capacitor during the first clock phase.