Abstract: A system and method for adaptive activity management of on-chip voltage regulators based upon the workload information is provided to force each on-chip regulator to operate in its most power-efficient load current. In the proposed regulator-gating technique, regulators are adaptively turned ON when the current demand is high and turned OFF when the current demand is low to improve the voltage conversion efficiency. With the proposed regulator-gating system and method, the overall voltage conversion efficiency from the battery or off-chip power supply to the output of the on-chip voltage regulators experiences an approximately 3 times improvement over the prior art techniques.

Abstract: A voltage-current conversion circuit for automatic test equipment (ATE) or a tester converts a low voltage, low current output from a power supply of the tester to a high voltage and/or high current output to be coupled to a device under test (DUT) while maintaining the sense capability of the tester power supply. In some embodiments, the voltage-current conversion circuit is implemented as a current only conversion circuit.

Abstract: A system is disclosed, which may include a differential charge pump. The differential charge pump may include a first and a second H-bridge circuit, each driving, on a respective output, an output current that is substantially similar over an output voltage operating range. The differential charge pump may be designed to receive increment, decrement and bias signals, and drive, in response to the increment and decrement signals, the output current to draw each H-bridge circuit output towards a first or a second supply voltage. The differential charge pump may also be designed to increase, in response to the bias signals, the output voltage operating range over which the output current is substantially similar. The differential charge pump may also include a bias signal generator, designed to generate bias signals in response to H-bridge circuit output voltages.

Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.

Abstract: A charge pump system includes a charge pump, a switchable impedance, a comparator, and a capacitor. The switchable impedance has an input coupled to the output of the charge pump. The comparator has a first input coupled to the output of the switchable impedance, a second input coupled to a reference, and an output coupled to the input of the charge pump. The capacitor has a first terminal coupled to the output of the charge pump and a second terminal coupled to the first input of the comparator. The switchable impedance causes a first impedance between the first and second terminals of the capacitor during a start-up operation of the charge pump system and a second impedance between the first and second terminals of the capacitor during a steady-state operation of the charge pump system, wherein the first impedance is lower than the second impedance.

Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller generates a power voltage signal. The semiconductor device generates a power-up signal in response to the power voltage signal, generates a first selection pulse, a second selection pulse and an initialization pulse signal, generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse.

Abstract: Disclosed is a semiconductor device that includes an N-channel MOS transistor and a control voltage generation circuit. The N-channel MOS transistor controls the supply of a power supply voltage obtained by stepping down a DC voltage. The control voltage generation circuit clips the gate voltage of the N-channel MOS transistor at a control voltage not higher than a predetermined voltage in accordance with the DC voltage.

Abstract: A bipolar output charge pump circuit 100 having a network of switching paths 110 for selectively connecting an input node (VV) and a reference node (VG) for connection to an input voltage, a first pair of output nodes (VP, VN) and a second pair of output nodes (VQ, VM), and two pairs of flying capacitor nodes (CF1A, CF1 B; CF2A, CF2B), and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors (CF1, CF2) connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes (VP, VN) and a second bipolar output voltage at the second pair of bipolar output nodes (VQ, VM).

Abstract: A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element.

Abstract: Methods and apparatus, including computer program products, are provided for filtering. In some example embodiments, there is provided an apparatus including a first differential amplifier including a first positive input, a first negative input, and a first output, wherein the first positive input is connected to the first output via at least a first capacitor, and wherein the first negative input is connected to the first output via at least a first resistor; and a second differential amplifier including a second input, a third input, and a second output, wherein the second input is connected to the second output via at least a third resistor, wherein the third input is connected to the second output via at least a second capacitor, and wherein an input is connected to the first positive input and the second input via at least a third capacitor. Related apparatus, systems, methods, and articles are also described.

Abstract: Integrated circuit designs and methods using adaptive dynamic voltage scaling circuits for IC designs that compensate for some of the effects of PVT dependent characteristics on the fabrication of advanced IC's but allow lower margins and provide high die yields, smaller die size, and lower power usage. An inner control loop varies the voltage output of an internal variable voltage regulator powered by an IC circuit voltage, and monitors the operation of a test circuit until it reaches a cross-over point (i.e., either fails to operate or begins to operate) with respect to an essentially identical nearby reference circuit, at which point the IC circuit voltage is adjusted by an outer control circuit to that voltage output level plus a margin.

Abstract: Provided are an operating method of a semiconductor integrated circuit and a semiconductor integrated circuit which includes a core circuit. The operating method includes: monitoring respective residencies of operating states of the core circuit; and controlling the operating states of the core circuit according to the monitored residencies of the operating states.

Abstract: An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a common mode capacitor, a first switch, a second switch, and a common mode potential adjustment circuit. The receiver includes a first channel for receiving a first channel voltage, and a second channel for receiving a second channel voltage. The common mode capacitor provides a common mode potential. The first switch electrically connects the first terminal resistor to the common mode capacitor, and the second switch electrically connects the second terminal resistor to the common mode capacitor. The common mode potential adjustment circuit is coupled to the first switch, the second switch and the common mode capacitor, and adjusts the common mode potential according to the first channel voltage and the second channel voltage.

Abstract: The present inventive concept is a hyuntak transistor that can prevent a thermal runaway phenomenon and a low heat high efficiency constant current circuit using an auxiliary transistor capable of a high amplification and a constant current. The circuit may be applied to drive a LED and a motor.

Abstract: In various embodiments a circuit is provided which may include a node at which a circuit potential may be provided; an alternating voltage providing circuit configured to provide a DC current free alternating voltage; a rectifier coupled to the alternating voltage providing circuit, the rectifier including a first rectifier terminal and a second rectifier terminal, wherein the first rectifier terminal or the second rectifier terminal may be coupled to the node; and a first output terminal and a second output terminal, wherein the first output terminal may be coupled to the first rectifier terminal to provide a first potential and wherein the second output terminal may be coupled to the second rectifier terminal to provide a second potential different from the first potential, the difference between the first potential and the second potential defining an output voltage, wherein the output voltage may be constant independent of the circuit potential.

Abstract: A reduced oxide stress cascode stack circuit includes a cascade transistor stack and dynamic bias circuits that supply an output voltage having a magnitude greater than an oxide reliability voltage of their component transistors. The reduced oxide stress cascode stack circuit also includes an offset voltage generator that provides an offset voltage based on a transient extreme of the output voltage, wherein the offset voltage is applied to the cascade transistor stack and the dynamic bias circuits to reduce component transistor voltages commensurate with the oxide reliability voltage. The reduced oxide stress cascode stack circuit further includes a bias voltage supply that modifies a bias voltage value of the cascade transistor stack and dynamic bias circuits by an amount proportional to the offset voltage. A method of reducing oxide stress in a cascode stack circuit is also provided.

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit.

Abstract: Systems and methods for authenticating electronic devices may perform one or more operations including, but not limited to: receiving at least one code associated with an authorization to perform one or more manufacturing life-cycle operations for at least one electronic device; and blowing one or more fuses of the at least one electronic device according to the at least one code associated with an authorization to perform one or more manufacturing life-cycle operations for the at least one electronic device.

Abstract: In one embodiment, to maintain the operation stability of a semiconductor device even when an external voltage changes. An input signal discrimination unit operates with a power supply potential supplied from a first power supply line VDDI. The input signal discrimination unit compares an input signal VIN with a reference potential Vref. The comparison result is inverted into a signal V0 by an inverter INV1. A power supply sensor circuit monitors the potential of the first power supply line VDDI. If an external potential VDDI falls below a reference potential VX, the power supply sensor circuit turns on a second current source. When the second current source is turned on, an operating current is supplied to a discrimination unit from the second current source as well as a first current source.

Abstract: An active noise cancellation device (2) for a medical device includes an active circuit having a first input connection (8), a second input connection (10), and an output connection (12). The second input connection (10) is connected to at least one predetermined reference signal. The active noise cancellation device (2) further includes a low-impedance body connection electrode (4) adapted to be in electrical contact with a bloodstream of a subject, wherein the low-impedance body connection electrode (4) is connected to said first input connection (8), and a feedback branch (14) connecting the output connection (12) with the first input connection (8). The feedback branch (14) comprises a current limiting circuit (18) to limit a current through said feedback branch (14) to be lower than a predetermined current.