Patents Examined by Jeffrey Zweizig
  • Patent number: 9106186
    Abstract: An amplifier biasing circuit that reduces gain variation in short channel amplifiers, an amplifier biasing circuit that produces a constant Gm biasing signal for short channel amplifiers, and a multistage amplifier that advantageously incorporates embodiment of both types of amplifier biasing circuits are described. Both amplifier biasing circuit approaches use an operational amplifier to equalize internal bias circuit voltages. The constant Gm biasing circuit produces a Gm of 1/R, where R is the value of a trim variable resistor value. The biasing circuit that reduces gain variation produces a Gm of approximately 1/R, where R is the value of a trim variable resistor value, however, the biasing circuit is configurable to adjust the bias circuit Gm to mitigate the impact of a wide range of circuit specific characteristics and a wide range of changes in the operational environment in which the circuit can be used, such as changes in temperature.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: August 11, 2015
    Assignee: Marvell International Ltd.
    Inventors: David M. Signoff, Wayne A. Loeb
  • Patent number: 9088159
    Abstract: A limiting circuit for at least one semiconductor transistor. The circuit includes a limiting path which is coupled between a first power terminal and a second power terminal of the semiconductor transistor. The limiting path includes a limiting transistor. A node of the limiting path located between the limiting transistor and the second power terminal of the semiconductor transistor is coupled to a control terminal of the semiconductor transistor. A voltage source is coupled to the control terminal of the limiting transistor and is designed to apply a control voltage to said control terminal of the limiting transistor. The control voltage corresponds to a critical voltage for the voltage between the first power terminal and the second power terminal of the semiconductor transistor. The limiting transistor is switched to a conductive state when said critical voltage is exceeded at a power terminal of said limiting transistor.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: July 21, 2015
    Assignee: Robert Bosch GmbH
    Inventor: Thomas Peuser
  • Patent number: 9085732
    Abstract: Chlorosilicate-based phosphors configured to emit yellow-green light in a wavelength ranging from about 500 nm to about 560 nm in response to an excitation source emitting at about 400 nm to about 480 nm, wherein the light emitted by the phosphor has a decay time ranging from about 1 millisecond (1 ms) to about 10 milliseconds (10 ms). The phosphor comprises a compound of the family Ca8-x-yAxEuyMg1-m-nBmMnn(Si1-sCsO4)4R2, where A is at least one divalent cation including Ca, Sr, Ba; B is Zn or Cd, or a divalent metal ion other than an alkaline earth; C is a cation, including at least one of Ge, Al, B, Gd, Ga, and N, and R is an anion, including F, Cl, Br, I, all respectively either individually, or in combinations.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: July 21, 2015
    Assignee: Intematix Corporation
    Inventors: Qinghua Zeng, Gang Wang, Yi-Qun Li
  • Patent number: 9083347
    Abstract: Circuits and methods for capturing internal signal values in a circuit before, during, and after a trigger event are disclosed. For example, a circuit can include a shift register configured to receive data values of an input data set over a plurality of cycles, and a counter unit configured to receive a trigger signal and to output the trigger signal after a number of cycles following the receiving of the trigger signal, where the trigger signal indicates a trigger event. The circuit can also include a switch configured to receive the trigger signal from the counter unit and to open a connection between an input interface and the shift register in response to receiving the trigger signal.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: July 14, 2015
    Assignee: XILINX, INC.
    Inventors: Riyas Noorudeen Remla, Rajesh Bansal
  • Patent number: 9081396
    Abstract: A voltage divider circuit is provided that automatically and dynamically adjusts its voltage divider chains as a supply voltage changes. The voltage divider circuit includes a plurality of voltage divider branches having different divider factors to divide the supply voltage and obtain a divided supply voltage. Additionally, a control circuit is coupled to the plurality of voltage divider branches and adapted to automatically monitor the supply voltage and dynamically select a voltage divider branch from among the plurality of voltage divider branches to maintain a selected divided supply voltage within a pre-determined voltage range.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 14, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Bo Sun
  • Patent number: 9075608
    Abstract: An integrated circuit comprising: a first core circuit configured to operate at a first clock rate for carrying out a first range of tasks; and a second core circuit configured to operate in a first mode and a second mode, the second core circuit being configured to operate at a second clock rate for carrying out a second range of tasks in the second mode and being configured to operate in the second mode when the first core circuit carries out the first range of tasks, the second clock rate being greater than the first clock rate.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: July 7, 2015
    Assignee: CAMBRIDGE SILICON RADIO LIMITED
    Inventors: Simon Finch, Alan Coombs
  • Patent number: 9070546
    Abstract: Provided is a semiconductor device in which change in characteristics of a transistor is suppressed and an output signal is changed sharply without increasing W/L of the transistor can be provided. Two transistors are connected in parallel between a wiring to which a low potential is supplied and an output terminal. When the low potential is output from the output terminal, both of the two transistors are turned on and then one of them is turned off. Thus, change in characteristics of the transistor can be suppressed and an output signal can be changed sharply without increasing W/L of the transistor.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: June 30, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 9067768
    Abstract: The present invention provides devices and methods for remotely illuminating the hook assembly and/or other load-end portions (e.g., a ball hook, block hook, crane spreader-bar and the like) of a crane rigging.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: June 30, 2015
    Assignee: Construction Innovations, Inc.
    Inventors: Todd Johnson, Glen J. Harmon
  • Patent number: 9054669
    Abstract: In an embodiment of the disclosure, an electronic device arranged for eliminating wireless noise interference is provided. The electronic device includes a circuit board and two first metal components. The metal components are arranged on different sides of the circuit board. Each of the first metal components comprises a first terminal and a second terminal opposite to the first terminal. The first terminal is coupled to the circuit board and the second terminal is open loop. The length of the first metal component is about one-fourth wavelength of a pre-determined frequency.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: June 9, 2015
    Assignee: MEDIATEK INC.
    Inventors: Hsiao-Ting Huang, Cheng-Hao Kuo
  • Patent number: 9049501
    Abstract: An electrical apparatus to sense current through a load includes a first input terminal having a first input voltage relative to a reference, a second input terminal having a second input voltage relative to the reference, a first load terminal of the load having a first load voltage relative to the reference, a second load terminal of the load having a second load voltage relative to the reference, a first current sensing element connected between the first input terminal and the first load terminal and a second current sensing element connected between the second input terminal and the second load terminal. A first sense voltage is determined by a relationship between the first input voltage and the second load voltage and a second sense voltage is determined by a relationship between the second input voltage and the first load voltage.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: June 2, 2015
    Assignee: Bose Corporation
    Inventors: Kenneth B. Delpapa, Michael B. Nussbaum, Jay N. Teixeira, George Nichols, Thomas A. Froeschle
  • Patent number: 9046908
    Abstract: A calibration method and apparatus for current and resistance are provided, where the current calibration method includes: injecting at least one portion of a set of predetermined compensation currents into at least one of an output current of a first current source and an output current of a second current source, and dynamically adjusting a distribution of the at least one portion of the set of predetermined compensation currents until two monitored voltage drops are equal to each other, and recording a first compensation current configuration; exchanging the first and second current sources, and dynamically adjusting the distribution of the at least one portion of the set of predetermined compensation currents until the two monitored voltage drops are equal to each other, and recording a second compensation current configuration; and according to the first and second compensation current configurations, generating a resultant compensation current, for use of current compensation.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: June 2, 2015
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Zhichao Gong, Hong-Sing Kao
  • Patent number: 9048817
    Abstract: An apparatus for active feed forward electromagnetic interference (EMI) filtering, including, a noise detection and current reconstruction circuit that receives EMI noise occurring at a noise source, and noise voltage compensation circuit operatively coupled to the noise detection and current reconstruction circuits. The active feed forward circuit generates a noise voltage compensation signal based on the EMI noise reconstructed by the noise detection circuit.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: June 2, 2015
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Miaosen Shen
  • Patent number: 9046912
    Abstract: A system and method for prolonging and equalizing the effective life of a plurality of transistors operating in parallel. The temperature of each transistor is measured and compared with the average temperature of the transistor system. A temperature difference is determined between the average temperature of the transistors and the measured temperature of each of the transistors. The gate resistance and the gate emitter resistance of each transistor is varied based on the temperature differences to control the measured temperature of each transistors by controlling current through each transistor thereby thermally balancing the transistors.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: June 2, 2015
    Assignee: The Boeing Company
    Inventors: Shengyi Liu, Lijun Gao, Eugene V. Solodovnik, Kamiar J. Karimi
  • Patent number: 9035725
    Abstract: An acoustic wave device includes a piezoelectric substrate, an interdigital transducer (IDT) electrode provided on an upper surface of the piezoelectric substrate, a first dielectric film covering the upper surface of the piezoelectric substrate to cover the IDT electrode, and a second dielectric film covering an upper surface of the first dielectric film. The second dielectric film includes a thin portion positioned in a tip region of electrode fingers of the IDT electrode and a thick portion which is positioned in a middle region of the IDT electrode and is thicker than the thin portion. The acoustic wave device suppresses spurious emission and has superior passband characteristics.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: May 19, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Tomoya Komatsu, Tomohiro Iwasaki, Hiroyuki Nakamura, Masahiro Yasumi, Kazunori Nishimura
  • Patent number: 9035694
    Abstract: Provided is a circuit for generating a reference voltage. The circuit includes a band gap circuit generating a first current having a size that increases in proportion to an absolute temperature and a second current having a size that decreases in proportion to the absolute temperature, and outputting a reference voltage based on the first current and the second current; a mirroring circuit mirroring a sum of the first current and the second current and outputting a mirroring voltage that is in proportion to the sum of the first current and the second current; and a start-up circuit receiving the mirroring voltage from the mirroring circuit and providing a driving current for generating the first current or the second current to the band gap circuit until a time when the first current starts to be generated in the band gap circuit.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 19, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Michael Choi, Marutha Muthu Muthuveeran
  • Patent number: 9035575
    Abstract: A lighting device using an LED is provided where an LED lighting device having an improved modulation depth which is calculated with the maximum value and the minimum value of an amount of instantaneous light emission in an AC-driven LED lighting device having an LED turned on and off by using an instantaneous AC voltage periodically varied with time.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: May 19, 2015
    Inventor: Dong-Won Lee
  • Patent number: 9013252
    Abstract: A dielectric-loaded cavity resonator has a conductive (e.g., copper) box defining a cavity and a dielectric (e.g., ceramic) resonator mounted within the box. The dielectric resonator has a cylindrical dielectric post and first and second dielectric pedestals respectively connected to the ends of the post and having lateral dimensions greater than the diameter of the post. Insulating (e.g., PTFE) pads are mounted onto outer surfaces of the pedestals to provide air gaps between the pedestals and corresponding top and bottom walls of the box. In certain embodiments, the pedestals have rectilinear, 3D shapes completely or only partially covering the top and bottom walls of the cavity, while, in other embodiments, the pedestals have cylindrical shapes maximally or less than maximally covering the top and bottom walls of the cavity.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: April 21, 2015
    Assignee: Alcatel Lucent
    Inventors: Tsu-Wei Lin, Noriaki Kaneda
  • Patent number: 9013231
    Abstract: In a bandgap voltage reference with low package shift, a proportional to absolute temperature (PTAT) voltage is generated using a single diode biased at two different current levels at two different times. Using the same diode for both current density measurements removes the absolute value of the base-emitter junction voltage (Vbe) and any package shift in the PTAT voltage. The bandgap voltage reference can be implemented in a single or differential circuit topology. In some implementations, the bandgap voltage reference can include circuitry for curvature correction.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: April 21, 2015
    Assignee: Atmel Corporation
    Inventors: Danut Manea, Jeff Kotowski, Scott N. Fritz, Yongliang Wang
  • Patent number: 9000864
    Abstract: A directional coupler for use in a predetermined frequency band includes a laminate body including a laminate of a plurality of insulation layers, a first terminal through a fourth terminal disposed on a surface of the laminate body, a main line connected between the first terminal and the second terminal and disposed on the insulation layer, a first sub-line connected to the third terminal, electromagnetically coupled with the main line, and disposed on the insulation layer, a second sub-line connected to the fourth terminal, electromagnetically coupled with the main line, and disposed on the second sub-line, and a phase adjusting circuit connected between the first sub-line and the second sub-line and configured to cause a phase shift on a passing signal. The main line, the first sub-line and the second sub-line do not overlap each other in a plan view from a direction of lamination.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: April 7, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Akira Tanaka
  • Patent number: 9000840
    Abstract: An integrated with a block including first and second oppositely doped semiconductor wells. There are standard cells placed next to one another, each standard cell including first transistors and a clock tree cell encircled by standard cells. The clock tree cell has a third semiconductor well with the same doping type as the doping of the first well and second transistors. The clock tree cell also has a semiconductor strip extending continuously around the third well and having the opposite doping type to the doping of the third well to electrically isolate the third well from the first well.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 7, 2015
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroeletronics SA, STMicroeletronics (Crolles 2) SAS
    Inventors: Yvain Thonnart, Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel