Abstract: A system which may be implemented on an integrated circuit including a global supply bus, a gated supply bus, a functional circuit receiving voltage from the gated supply bus, and a digital power gating system. The digital power gating system includes gating devices, a power gating control system, and a global control adjuster. The gating devices are coupled between the global and gated supply buses and are controlled by a digital control value. The power gating control system performs power gating by successively adjusting the digital control value to reduce a voltage of the gated supply bus to a state retention voltage level. The global control adjuster performs a global adjustment of the digital control value to increase the voltage of the gated supply bus to prevent it from falling below the state retention voltage level in response to an impending change of a voltage of the global supply bus.

Abstract: An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.

Abstract: A reference voltage generating circuit with extremely low temperature dependence is provided. The reference voltage generating circuit includes a BGR circuit which generates a bandgap reference voltage; a bandgap current generating circuit which generates a bandgap current according to the bandgap reference voltage; a PTAT current generating circuit which generates a current proportional to the absolute temperature; and a linear approximate correction current generating circuit which compares the current generated by the PTAT current generating circuit and the bandgap current to generate a correction current, and the BGR circuit adds, to the bandgap reference voltage, a correction voltage generated based on the correction current.

Abstract: Exemplary embodiments disclose a semiconductor device which includes a function block including a plurality of transistors; a temperature detector configured to detect a driving temperature of the function block in real time; and an adaptive body bias generator configured to provide a body bias voltage to adaptively adjust leakage currents of the transistors according to the detected driving temperature, wherein the adaptive body bias generator is further configured to generate a body bias voltage corresponding to a predetermined minimum leakage current according to the driving temperature.

Abstract: In one embodiment, an LED current controller is formed to determine which of a plurality of LED branches has the largest voltage drop and to select the current through that branch to use in controlling the value of current that flows through other LED branches.

Abstract: High voltage rated isolation capacitors are formed on a face of a primary integrated circuit die. The isolation capacitors AC couple the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitors DC isolate the primary integrated circuit from the second integrated circuit die. Isolated power transfer from the first voltage domain to the second voltage domain is provided through the high voltage rated isolation capacitors with an AC oscillator or PWM generator. The AC oscillator voltage amplitude may be increased for an increase in power through the high voltage rated isolation capacitors, and a larger value capacitor in the second voltage domain may provide for peak current demand from circuits in the second voltage domain.

Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.

Abstract: A building lighting control system includes a central building server, distributed zone controllers, and light sensors and control units in each zone. Using occupant lighting preferences, occupancy state, and light levels, each zone controller computes a utility curve which represents the relationship between energy use and service level in the zone. The building server zone receives utility curves from all the zones and allocates energy units to the zones based on the utility curves using a utility-based trading algorithm in order to optimize service levels with minimal energy. Each zone controller then distributes energy to lights in its zone based on energy units allocated to the zone by the building server and based also on influence matrices representing the influences of the lights in the zone upon the sensors in the zone. The building server may also compute and output long-term operational information of the building.

Abstract: A charge pump circuit using a voltage doubler-type of circuitry for generating an output voltage is described. An output generating stage uses a voltage double structure, except that the transistors in each leg are not cross-coupled to the other leg, but instead are controlled by an auxiliary section. The auxiliary section has a voltage doubler structure, but is not used to drive the load, but instead provides the gate voltage for the precharge section using the same levels as used for the corresponding transistors in the auxiliary section. This arrangement can be particularly advantageous for applications using low supply voltages to address self-loading effect due to loading. As the auxiliary section does not drive the load, its elements can be sized smaller. Additional improvement can be obtained by using separate clock drivers for the auxiliary section to address secondary self-loading effect due to loading.

Abstract: An offset-compensation circuit in a MEMS sensor device, provided with a micromechanical detection structure that transduces a quantity to be detected into an electrical detection quantity, and with an electronic reading circuit, coupled to the micromechanical detection structure for processing the electrical detection quantity and supplying an output signal, which is a function of the quantity to be detected. A compensation structure is electrically coupled to the input of the electronic reading circuit and can be controlled for generating an electrical compensation quantity, of a trimmable value, for compensating an offset on the output signal; the compensation circuit has a control unit, which reads the output signal during operation of the MEMS sensor device; obtains information on the offset present on the output signal itself; and controls the compensation structure as a function of the offset information.

Abstract: A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.

Abstract: A high-speed low-power latch includes three sets of transistors. A first set of transistors selects a tracking mode or a holding mode for the latch based on a clock signal having non-rail-to-rail or rail-to-rail voltage swing. A second set of transistors captures a data value based on an input signal and provides an output signal during the tracking mode. A third set of transistors stores the data value and provides the output signal during the holding mode. The input and output signals have rail-to-rail voltage swing. In another aspect, a signal generator includes at least one latch and a control circuit. The latch(es) receive a clock signal and generate an output signal. The control circuit senses a duty cycle of a feedback signal derived from the output signal and generates a control signal to adjust operation of the latch(es) to obtain 50% duty cycle for the feedback signal.

Abstract: A circuit includes a temperature sensor configured to determine a circuit temperature and includes an analog circuit including one or more controllable circuit elements. The analog circuit includes at least one adjustable parameter. The circuit further includes a controller coupled to the temperature sensor and configured to select a threshold temperature. The controller is configured to control the analog circuit in response to the circuit temperature to selectively adjust at least one adjustable parameter of the analog circuit when the temperature exceeds the selected threshold temperature.

Abstract: A circuit for providing connection between a first node at a first voltage and a second node at a second voltage. The circuit has a first inductive element having a first terminal coupled to the first node, a first switching element coupled between a second terminal of the first inductive element and the second node, a second inductive element having a first terminal configured for receiving current from the second terminal of the first inductive element, and having a second terminal coupled to a third node, and a second switching element coupled between the first terminal of the second inductive element and the second node. The first and second switching elements are configured for providing alternating current flow paths between the first node and the second node.

Abstract: A filter comprises an integrator, a signal feeding path, a first operational amplifier and a second capacitor. The integrator comprises a first input terminal and a first output terminal. The signal feeding path comprises: a first resistor, having a first terminal coupled to the first output terminal; a first capacitor, having a first terminal coupled to the second terminal of the first resistor; and a second resistor, having a first terminal coupled to the integrator and having a second terminal coupled to the second terminal of the first capacitor. The first operational amplifier comprises a second input terminal coupled to the second terminal of the first resistor and the first terminal of the first capacitor, and comprises a second output terminal. The second capacitor comprises a first terminal coupled to the second terminal of the first capacitor, and comprises a second terminal coupled to the second output terminal.

Abstract: Methods and systems for selecting content for outputting on a mobile device during a program break in an Internet radio stream using mobile device location information. In one aspect, the methods and systems seamlessly select content for outputting on a mobile device during a program break in an Internet radio stream using mobile device location information and program break markers. In another aspect, the methods and systems select content for outputting on a mobile device during a program break in an Internet radio stream using mobile device trajectory information.

Abstract: An active pen IC includes a plurality of pads coupled to receive a plurality of receive (RX) signals induced from a mobile device, the received RX signals constituting an original group of RX signals. The active pen IC also includes a permuting unit configured to permute the pads such that the received RX signals corresponding to the permuted pads constitute a generated group of RX signals.

Abstract: According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip.

Abstract: A semiconductor integrated circuit which includes a control circuit; and a power management integrated circuit (IC) configured to supply an operating voltage to the control circuit. The control circuit includes a clock generator; a processor unit; a temperature sensor; a body bias generator; and a controller. The controller controls the power management IC and the clock generator when temperature data indicates a temperature higher than a high temperature and controls the power management IC or the body bias generator when the temperature data indicates a temperature lower than a low temperature. The high temperature is lower than a hot temperature of the control circuit and the low temperature is higher than a cold temperature of the control circuit and lower than the high temperature.

Abstract: A charge distributor comprises a charge generator configured to output a charge, a current conveyor, and a plurality of output stages. The current conveyor is configured to receive the charge from the charge generator as an input and to couple this charge to a plurality of output stages. A first output stage, of the plurality of output stages, comprises a plurality of current mirrors. The plurality of current mirrors is configured to mirror and scale the charge received from the current conveyor into a scaled mirrored charge. The first output stage is configured to provide the scaled mirrored charge as an output.