Abstract: A device for supplying control signals to memory units of a memory module comprises a first bus section for supplying a first part of the control signals to a first memory unit. In addition, a second bus section is provided for supplying a second part of the control signals to a second memory unit. Finally, the device comprises redrive means for redriving the first part of the control signals from the first memory unit to the second memory unit and for redriving the second part of the control signals from the second memory unit to the first memory unit. A memory unit for such a device for supplying control signals comprises first inputs for receiving a first part of the control signals from a memory control, second inputs for receiving a second part of the control signals from at least one other memory unit, and outputs for redriving said first part of the control signals to said at least one other memory unit.

Abstract: A method and apparatus is described for controlling accesses to a shared resource. An arbitration mechanism uses a register, accessible by each device sharing the resource. The register may be written by the device to request access to the resource, and read by the device to determine whether access to the resource has been granted. Advantageously, the register includes an override bit, which may be used by either device to override the peer device's request for the shared resource. In addition, the register includes a reset bit that may be used to reset arbitration logic controlling the access to the shared logic. The register is used by a straightforward arbitration mechanism that includes only IDLE and GRANT states for each device coupled to the shared resource. Such an arrangement provides a low cost method of controlling accesses to a shared resource.

Abstract: A modular information handling system includes a KVM management card. The KVM management card manages KVM communication with associated blade servers and allows access to KVM signals from each of the associated blade server through a VGA connector, a first PS2 connector and a second PS2 connector.

Abstract: A system prevents disruption of one or more system buses. The system monitors communication on the one or more system buses during an input mode and an output mode and detects changes between the input mode and the output mode. The system determines whether a predetermined time period has elapsed after a change from the input mode to the output mode and changes from the output mode to the input mode when the predetermined time period has elapsed after a change from the input mode to the output mode.

Abstract: A method for detecting a timeout condition for a data item (e.g., a request) within the process (e.g., within an arbitration process) includes maintaining a current time as a first N-bit binary number (A). An event time of an occurrence of an event pertaining to the data item within the process is recorded and stored as a second N-bit binary number (B). A predetermined time limit, expressed as a non-negative integer K, is configured. K is less than N and K is a logarithm base 2 of the predetermined time limit. A timeout condition pertaining to the data item is detected when a difference between the current time and the event time exceeds the predetermined time limit. The detection of the timeout condition is performed utilizing a single-stage operation. This single stage operation may include computing A (current time)?B (event time) modulo 2n?2k.

Abstract: In a CPU, a FET is turned off and power is not supplied to a power supply element of a transceiver for a period of time until predetermined initialization processing, which is implemented in a peripheral device when power is supplied via a cable from a host PC, has been concluded (i.e., a period of time until it becomes possible for the peripheral device to initiate data communication with the host PC). Thus, even if the peripheral device and the host PC are physically connected by a cable, data signals transmitted along signal lines are not relayed by the transceiver to a logic controller, whereby it in effect becomes possible to set the peripheral device in a pseudo-non-connected state with respect to the host PC.

Abstract: A data processing system includes: at least one function module connected to a single system bus; a data transfer controller which outputs a first bus use permission request signal based on a data transfer request signal output from the at least one function module; a central processing unit connected to the system bus which outputs a second bus use permission request signal; an arbitration controller for determining, based on the first and second bus use permission request signals, which of the data transfer controller and the central processing unit should obtain a permission to use the system bus; a section for setting a first data amount which can be continuously transferred by the at least one function module; a section for suspending an output of the first bus use permission request signal to the arbitration controller for at least one clock cycle after a data transfer by the at least one function module is completed; and a section for giving the permission to use the system bus to one of the data trans

Abstract: Systems and methods of information transfer are disclosed. In one embodiment, the system may comprise a master device and a slave device coupled by a bus in which clock information is embedded in the data stream. Various flow control techniques may be used to compensate for differences in transfer rates supported by the master and slave devices. Two types of synchronization fields may be employed to establish and maintain clock acquisition. The master device may transfer information to the slave device using a sync field of a first type followed by a first data packet, and the slave device may respond to each data packet with a sync field of a second, different type, followed by a status ready field if no additional time is needed before receiving another data packet.

Abstract: A bus arbiter controls the bus frequency in a system that includes a plurality of bus masters and a plurality of slaves. The bus frequency is determined according to the internal frequency of the devices that are part of the transaction. Additionally, the bus frequency is set according to the length of the bus between the devices that are a part of the transaction and, correspondingly, the expected amount of impedance there between. As a part of the present invention, a master seeking bus resources to initiate a transaction generates a bus request and a destination address to the bus arbiter so that it may determine a corresponding bus frequency in advance. Thereafter, the bus arbiter sets the bus frequency to a value that corresponds to the transaction that is about to take place thereon. Next, the bus arbiter issues a grant signal to enable the master to use the bus. Each slave device for a transaction then generates or receives sample cycle signals indicating when a signal should be read on the bus.

Abstract: A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer.

Abstract: A method of sharing user resources in a computer system through a universal serial bus (USB) interface. The method may involve, not necessarily in this order, associating at least one USB device with a first user and at least another USB device with a second user; assigning the first user to a first USB port; assigning the second user to a second USB port; permitting the first user to temporarily assume control of the computer system through the first USB port for operation of the at least one USB device; and blocking the second user from access to the computer system while the first user has temporary control of the computer system.

Abstract: A filter driver (125) can communicate with the USB stack and controller and with the CardBay, CardBus, and flashmedia stack and controller. This can allow the use of a CardBay card in a CardBus socket in a manner that is transparent to the user.

Abstract: According to the claimed invention, the computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, and a south bridge electrically connected to the north bridge, the south bridge having a general purpose serial input/output port. The computer also includes at least one peripheral device electrically connected to the south bridge and an interfacing circuit for providing a plurality of extended general purpose input/output ports, the interfacing circuit having a connection end electrically connected to the general purpose serial input/output port. When inputting a data signal from a general purpose input/output (GPIO) port, the data signal is transmitted to the general purpose serial input/output port through the connection end of the interfacing circuit.

Abstract: Round robin arbitration system includes a first round robin arbitration module and a second round robin arbitration module. The first round robin arbitration module has a first bit width. It is configured to partition a plurality of requests into a plurality of blocks of requests, to select a block having one or more active requests using round robin arbitration, and to generate a first index corresponding to the selected block. The second round robin arbitration module has a second bit width. It is configured to store each request of the selected block, to select each active request of the selected block using round robin arbitration, to generate a second index corresponding to the selected active request, and to generate a first signal for synchronizing operation of the first and second modules. The round robin arbitration system has a bit width that is a product of the first and second bit widths.

Abstract: A method and system for managing distributed arbitration for multi-cycle data transfer requests provides improved performance in a processing system. A multi-cycle request indicator is provided to a slice arbiter and if a multi-cycle request is present, only one slice is granted its associated bus. The method further blocks any requests from other requesting slices having a lower latency than the first slice until the latency difference between the other requesting slices and the longest latency slice added to a predetermined cycle counter value has expired. The method also blocks further requests from the first slice until the predetermined cycle counter value has elapsed and blocks requests from slices having a higher latency than the first slice until the predetermined cycle counter value less the difference in latencies for the first slice and for the higher latency slice has elapsed.

Abstract: A method for use with a computer system includes permitting a first bus agent to access a bus during predetermined windows of time and preventing a second bus agent from accessing the bus outside of the windows. The first bus agent has a higher priority than the second bus agent. The method includes monitoring the use of the bus by the first bus agent during the window and the regulation durations of the windows are selectively regulated based on the use.

Abstract: When a device such as a printer is connected to a connector 49 via a USB cable using an electronic device 40 as a host, a selecting circuit 43b is switched to a host function circuit 43a by operating a switch 42. When a host such as a personal computer is connected to the connector 49 via the USB cable using the electronic device 40 as device, the selecting circuit 43b is switched to a device function circuit 44a by operating the switch 42. A USB interface is controlled according to output of a microcomputer 41. Therefore, an interface circuit which meets USB standards, facilitates switching between a host function and a device function, has a simple circuit configuration and allows small-sizing can be provided.

Abstract: System for protecting data on a data carrier on which is stored an accessible medium code and data only accessible after presenting an access code, comprises: a) an apparatus incorporating, a programmed processor, a user interface, a mobile telephone incorporating a SIM-card, b) a central station incorporating a further programmed processor cooperating with a number of memories storing valid medium SIM and access codes. The processor can be connected through the telephone and a suitable communication network to the further processor in the central station whereby the SIM-code of the telephone and the medium code of the carrier are transferred to the further processor to be processed into an access code. The resulting combination of codes is compared with codes stored in memories, and in case of a valid code combination a coded access permission is sent to the processor enabling the software to read data from the data carrier.